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For the Inventor, By the Inventor

Chandler, AZ, United States of America

Sri Ranga Sai Boyapati

This inventor holds 63 USPTO granted patents and 27 published patent applications and 4 EPO patents, primarily in High Density Interconnects (CPC class H01L). Top assignees: Intel Corporation, Tahoe Research, Ltd.. Active years: 2016-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sri Ranga Sai Boyapati. Retrieved from https://idiyas.com/inventor/sri-ranga-sai-boyapati

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 63 

% Patents Active = 90.5

 

Average Co-Inventor Count = 5.2

ph-index = 5

Forward Citations = 154(Granted Patents)

Forward Citations (Not Self Cited) = 119(Dec 10, 2025)


Inventors with similar research interests:


Company Filing History:

goldMedal62 out of 56,440 
 
Intel Corporation
 patents
silverMedal1 out of 86 
 
Tahoe Research, Ltd.
 patents

Years Active: 2016-2025

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Areas of Expertise:
Faraday Rotator
Magneto-Optical Kerr Effect
Photonic Packaging
Multi-Chip Package
Embedded Die
Electromigration Resistant
High Bandwidth
Lithographic Via Formation
Panel Level Packaging
Coaxial Interconnect
Thin Film Barrier
Variable Height Conductive Elements
63 patents (USPTO):Explore Patents
1. 12481108 - Faraday rotator interconnect as a through-via configuration in a patch architecture (2025-11-25),
2. 12253722 - Magneto-optical Kerr effect interconnects for photonic packaging (2025-03-18),
3. 12218071 - Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers (2025-02-04),
4. 12218069 - Multi-chip package with high density interconnects (2025-02-04),
5. 12176223 - Integrated circuit package supports (2024-12-24),
6. 12046560 - Microelectronic device with embedded die substrate on interposer (2024-07-23),
7. 11935857 - Surface finishes with low RBTV for fine and mixed bump pitch architectures (2024-03-19),
8. 11923307 - Microelectronic structures including bridges (2024-03-05),
9. 11908821 - Sacrificial dielectric for lithographic via formation to enable via scaling in high density interconnect packaging (2024-02-20),
10. 11908802 - Multi-chip package with high density interconnects (2024-02-20),
11. 11894324 - In-package RF waveguides as high bandwidth chip-to-chip interconnects and methods for using the same (2024-02-06),
12. 11894311 - Microelectronic device with embedded die substrate on interposer (2024-02-06),
13. 11862619 - Patch accommodating embedded dies having different thicknesses (2024-01-02),
14. 11854834 - Integrated circuit package supports (2023-12-26),
15. 11837534 - Substrate with variable height conductive and dielectric elements (2023-12-05),

Title: The Innovative Journey of Sri Ranga Sai Boyapati

Introduction:

Sri Ranga Sai Boyapati, a talented inventor based in Chandler, AZ, has been making significant contributions to the field of technology with his groundbreaking innovations.

Latest Patents:

Sri Ranga Sai Boyapati holds several patents in the areas of artificial intelligence, renewable energy, and medical devices, showcasing his diverse range of expertise and creativity.

Career Highlights:

With a background in engineering and a passion for problem-solving, Boyapati has successfully developed cutting-edge solutions that have the potential to revolutionize industries and improve the quality of life for many.

Collaborations:

Throughout his career, Sri Ranga Sai Boyapati has collaborated with leading research institutions, universities, and tech companies to bring his inventions to life, demonstrating his ability to work effectively in multidisciplinary teams.

Conclusion:

In conclusion, Sri Ranga Sai Boyapati stands out as a visionary inventor who continues to push the boundaries of innovation, inspiring others in the field to think outside the box and create a better future for all.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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