The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2024
Filed:
Dec. 28, 2021
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Kristof Darmawikarta, Chandler, AZ (US);
Sri Ranga Sai Boyapati, Chandler, AZ (US);
Hiroki Tanaka, Chandler, AZ (US);
Robert A. May, Chandler, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/538 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/19 (2013.01); H01L 21/481 (2013.01); H01L 21/4853 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/49866 (2013.01); H01L 23/5381 (2013.01); H01L 23/5386 (2013.01); H01L 24/20 (2013.01); H01L 2224/18 (2013.01);
Abstract
An apparatus, comprising a substrate comprising a dielectric, a conductor, comprising a via embedded within the dielectric, the via has a first end and a second end, and substantially vertical sidewalls between the first end and the second end, and a conductive structure extending laterally from the first end of the via over the dielectric, wherein the via and the conductive structure have a contiguous microstructure.