Intel Corporation

Tahoe Research, Ltd.

Sri Ranga Sai Boyapati

Robert Alan May

Kristof Darmawikarta

Srinivas V Pietambaram

Aleksandar Aleksov

Hiroki Tanaka

Amruthavalli Pallavi Alur

Robert L Sankman

Islam A Salama

Steve S Cho

Jung Kyu Han

Thomas Heaton

Ali Lehaf

Rahul N Manepalli

Javier Soto Gonzalez

Daniel N Sobieski

Adel A Elsherbini

Rahul Jain

Sheng C Li

Telesphor Kamgaing

Dilan Seneviratne

Andrew James Brown

Qinglei Zhang

Prithwish Chatterjee

Changhua Liu

Sashi S Kandanur

Chung Kwang Christopher Tan

Kwangmo Lim

Johanna M Swan

Ofir Degani

Omkar G Karhade

Nitin A Deshpande

Eyal Fayneh

Kyu Oh Lee

Brandon C Marin

Yikang Deng

Sai Vadlamani

Amanda E Schuckman

Lauren Ashley Link

Bai Nie

Lilia May

Ravindranadh T Eluri

Kwangmo Chris Lim

Chung Kwang Tan

Sandeep Gaan

Maroun D Moussallem

David Levy

Kristof Darmawaikarta

Kemal Aygun

Zhiguo Qian

Jeremy D Ecton

Gang Duan

Junnan Zhao

Tarek A Ibrahim

Wei-Lun Kane Jen

Ji Yong Park

Siddharth K Alur

Mark S Hlad

Praneeth Kumar Akkinepally

Xiaoqian Li

Frank Truong

Yosuke Kanaoka

Sameer Paital

Arnab Sarkar

Haobo Chen

Divya Pratap

Zheng Zhou

Robin Shea McRee

Kirstof Darmawikarta

Wei Lun Jen

Lisa Ying Ying Chen

Merve Celikkol

Omkar Karhade

Nitin Deshpande

Kristof Darmawkarta

Embodiments disclosed herein include optical systems with Faraday rotators in order to enhance efficiency. In an embodiment, a photonics package comprises an interposer and a patch over the interposer. In an embodiment, the patch overhangs an edge of the interposer. In an embodiment, the photonics package further comprises a photonics die on the patch and a Faraday rotator passing through a thickness of the patch. In an embodiment, the Faraday rotator is below the photonics die.

Faraday rotator interconnect as a through-via configuration in a patch architecture

An optical package comprising an optical die that is electrically coupled to a package substrate, and an optical interconnect adjacent the optical die. The optical interconnect comprises a first polarizing filter adjacent to a first lens, a second polarizing filter adjacent to a second lens; and a film comprising a magnetic material between the first polarizing filter and the second polarizing filter. The second polarizing filter is rotated with respect to the first polarizing filter and the magnetic material is to rotate a polarization vector of light incoming to the optical interconnect. An optical fiber interface port is immediately adjacent to the first lens. The second lens is immediately adjacent to an optical interface of the optical die.

Magneto-optical Kerr effect interconnects for photonic packaging

An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.

Multi-chip package with high density interconnects

A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.

Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers

Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, a method for forming an IC package support may include forming a first dielectric material having a surface; forming a first conductive via in the first dielectric material, wherein the first conductive via has tapered sidewalls with an angle that is equal to or less than 80 degrees relative to the surface of the first dielectric material; forming a second dielectric material, having a surface, on the first dielectric material; and forming a second conductive via in the second dielectric material, wherein the second conductive via is electrically coupled to the first conductive via, has tapered sidewalls with an angle that is greater than 80 degrees relative to the surface of the second dielectric material, and a maximum diameter between 2 microns and 20 microns.

Integrated circuit package supports

A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

Microelectronic device with embedded die substrate on interposer

Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

Surface finishes with low RBTV for fine and mixed bump pitch architectures

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Microelectronic structures including bridges

An apparatus, comprising a substrate comprising a dielectric, a conductor, comprising a via embedded within the dielectric, the via has a first end and a second end, and substantially vertical sidewalls between the first end and the second end, and a conductive structure extending laterally from the first end of the via over the dielectric, wherein the via and the conductive structure have a contiguous microstructure.

Sacrificial dielectric for lithographic via formation to enable via scaling in high density interconnect packaging

In-package radio frequency (RF) waveguides as high bandwidth chip-to-chip interconnects and methods for using the same are disclosed. In one example, an electronic package includes a package substrate, first and second silicon dies or tiles, and an RF waveguide. The first and second silicon dies or tiles are attached to the package substrate. The RF waveguide is formed in the package substrate and interconnects the first silicon die or tile with the second silicon die or tile.

In-package RF waveguides as high bandwidth chip-to-chip interconnects and methods for using the same

Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.

Patch accommodating embedded dies having different thicknesses

Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.

Apparatuses, systems and methods associated with package substrate design with variable height conductive elements within a single layer are disclosed herein. In embodiments, a substrate may include a first layer, wherein a trench is located in the first layer, and a second layer located on a surface of the first layer. The substrate may further include a first conductive element located in a first portion of the second layer adjacent to the trench, wherein the first conductive element extends to fill the trench, and a second conductive element located in a second portion of the second layer, wherein the second conductive element is located on the surface of the first layer. Other embodiments may be described and/or claimed.

Substrate with variable height conductive and dielectric elements

Growing community of inventors

Chandler, AZ, United States of America

Sri Ranga Sai Boyapati