Peter G Tolchinsky

This inventor holds 28 USPTO granted patents and 2 published patent applications and 1 EPO patent, primarily in Semiconductor Technology. Top assignees: Intel Corporation, Siltronic Ag. Active years: 2005-2020.

USPTO Granted Patents = 28 (Patent Applications = 2)

% Patents Active = 28.6

EPO Patents = 1 (Patent Applications = 2)

Average Co-Inventor Count = 4.5

ph-index = 8

Forward Citations = 633(Granted Patents)

Location History:

Portland, OR (US) (2006)
Beaverton, OR (US) (2005 - 2020)

Company Filing History:

where one patent can have more than one assignee

Years Active: 2005-2020

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Areas of Expertise:

Monolithic Co-Integration

GaN Devices

Silicon PMOS

Voltage Regulation

Hetero-Layers

Epitaxial Wafer

Nanowires

Stacking Fault

High Hole Mobility

Buffer Layers

Quantum Well Structure

Silicon-On-Insulator

28 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 10879134 - Techniques for monolithic co-integration of silicon and III-N semiconductor transistors (2020-12-29),

2. 10692839 - GaN devices on engineered silicon substrates (2020-06-23),

3. 10600787 - Silicon PMOS with gallium nitride NMOS for voltage regulation (2020-03-24),

4. 9711591 - Methods of forming hetero-layers with reduced surface roughness and bulk defect density of non-native surfaces and the structures formed thereby (2017-07-18),

5. 9691843 - Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition (2017-06-27),

6. 9691632 - Epitaxial wafer and a method of manufacturing thereof (2017-06-27),

7. 9559160 - Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition (2017-01-31),

8. 8617945 - Stacking fault and twin blocking barrier for integrating III-V on Si (2013-12-31),

9. 8217383 - High hole mobility p-channel Ge transistor structure on Si substrate (2012-07-10),

10. 8143646 - Stacking fault and twin blocking barrier for integrating III-V on Si (2012-03-27),

11. 7863710 - Dislocation removal from a group III-V film grown on a semiconductor substrate (2011-01-04),

12. 7851781 - Buffer layers for device isolation of devices grown on silicon (2010-12-14),

13. 7791063 - High hole mobility p-channel Ge transistor structure on Si substrate (2010-09-07),

14. 7687799 - Methods of forming buffer layer architecture on silicon and structures formed thereby (2010-03-30),

15. 7670928 - Ultra-thin oxide bonding for S1 to S1 dual orientation bonding (2010-03-02),

Title: The Innovative Journey of Peter G Tolchinsky

Introduction:

Peter G Tolchinsky, a visionary inventor based in Beaverton, Oregon, has made significant contributions to the field of technology through his groundbreaking inventions and patents.

Latest Patents:

Peter G Tolchinsky's latest patents include cutting-edge technologies in the fields of artificial intelligence, renewable energy, and sustainable materials. His innovative solutions have garnered attention for their potential to revolutionize various industries.

Career Highlights:

With a career spanning over two decades, Peter G Tolchinsky has established himself as a leading figure in the world of innovation. His work has been recognized with numerous awards and accolades, solidifying his reputation as a pioneer in his field.

Collaborations:

Throughout his career, Peter G Tolchinsky has collaborated with top research institutions, leading companies, and brilliant minds in the industry. These collaborations have not only enriched his work but have also led to the development of groundbreaking technologies that have the potential to shape the future.

Conclusion:

In conclusion, Peter G Tolchinsky's relentless pursuit of innovation and his passion for creating solutions to complex problems have cemented his legacy as a true visionary in the world of inventions. His contributions continue to inspire and drive progress in the ever-evolving landscape of technology.