The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 2010

Filed:

Jun. 19, 2008
Applicants:

Mantu K. Hudait, Portland, OR (US);

Peter G. Tolchinsky, Beaverton, OR (US);

Loren A. Chow, Santa Clara, CA (US);

Dmitri Loubychev, Bethlehem, PA (US);

Joel M. Fastenau, Bethlehem, PA (US);

Amy W. K. Liu, Mountain View, CA (US);

Inventors:

Mantu K. Hudait, Portland, OR (US);

Peter G. Tolchinsky, Beaverton, OR (US);

Loren A. Chow, Santa Clara, CA (US);

Dmitri Loubychev, Bethlehem, PA (US);

Joel M. Fastenau, Bethlehem, PA (US);

Amy W. K. Liu, Mountain View, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/00 (2006.01); H01L 21/338 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a GaSb nucleation layer on a substrate, forming a Ga(Al)AsSb buffer layer on the GaSb nucleation layer, forming an InAlAs bottom barrier layer on the Ga(Al)AsSb buffer layer, and forming a graded InAlAs layer on the InAlAs bottom barrier layer thus enabling the fabrication of low defect, device grade InGaAs based quantum well structures.


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