The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2012
Filed:
Sep. 07, 2010
Mantu K. Hudait, Portland, OR (US);
Suman Datta, Port Matilda, PA (US);
Jack T. Kavalieros, Portland, OR (US);
Peter G. Tolchinsky, Beaverton, OR (US);
Mantu K. Hudait, Portland, OR (US);
Suman Datta, Port Matilda, PA (US);
Jack T. Kavalieros, Portland, OR (US);
Peter G. Tolchinsky, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium ('Ge') transistor structure on a Silicon ('Si') substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.