Intel Corporation

Siltronic Ag

Peter G Tolchinsky

Mohamad A Shaheen

Irwin Yablok

Mantu K Hudait

Loren A Chow

Joel Mark Fastenau

Dmitri Loubychev

Amy W K Liu

Jack T Kavalieros

Marko Radosavljevic

Robert S Chau

Van H Le

Han Wui Then

Sansaptak W Dasgupta

Suman Datta

Brian S Doyle

Glenn A Glass

Kelin J Kuhn

Chuan Hu

Annalisa Cappellani

Ryan Lei

Richard D Emery

Willy Rachmady

Matthew V Metz

Niloy Mukherjee

Benjamin Chu-Kung

Mark T Bohr

Valluri Ramana Rao

Roza Kotlyar

Niti Goel

Martin D Giles

Michael L McSwiney

James M Powers

Peter Storck

Norbert Werner

Martin Vorderwestner

Suman Dutta

David Simon, Legal Representative

Scott R List

Mark R Lemay

Techniques are disclosed for monolithic co-integration of silicon (Si)-based transistor devices and III-N semiconductor-based transistor devices over a commonly shared semiconductor substrate. In accordance with some embodiments, the disclosed techniques may be used to provide a silicon-on-insulator (SOI) or other semiconductor-on-insulator structure including: (1) a Si (111) surface available for formation of III-N-based n-channel devices; and (2) a Si (100) surface available for formation of Si-based p-channel devices, n-channel devices, or both. Further processing may be performed, in accordance with some embodiments, to provide n-channel and p-channel devices over the Si (111) and Si (100) surfaces, as desired. In accordance with some embodiments, the disclosed techniques may be used to provide co-integrated III-N-based n-type metal-oxide-semiconductor (NMOS) devices and Si-based p-type metal-oxide-semiconductor (PMOS), NMOS, or complementary MOS (CMOS) devices with different step heights or with a given degree of co-planarity, as desired for a given target application or end-use.

Techniques for monolithic co-integration of silicon and III-N semiconductor transistors

GaN-On-Silicon (GOS) structures and techniques for accommodating and/or controlling stress/strain incurred during III-N growth on a large diameter silicon substrate. A back-side of a silicon substrate may be processed to adapt substrates of standardized diameters and thicknesses to GOS applications. Bowing and/or warping during high temperature epitaxial growth processes may be mitigated by pre-processing silicon substrate so as to pre-stress the substrate in a manner than counterbalances stress induced by the III-N material and/or improve a substrate's ability to absorb stress. III-N devices fabricated on an engineered GOS substrate may be integrated together with silicon MOS devices fabricated on a separate substrate. Structures employed to improve substrate resilience and/or counterbalance the substrate stress induced by the III-N material may be further employed for interconnecting the III-N and silicon MOS devices of a 3D IC.

GaN devices on engineered silicon substrates

This disclosure pertains to a gallium nitride transistor that is formed in a trench etched into a silicon substrate. A gallium nitride layer is on the trench of the silicon substrate. A source electrode and a drain electrode reside on the gallium nitride layer. A gate electrode resides on the gallium nitride layer between the source electrode and the drain electrode. A first polarization layer resides on the gallium nitride layer between the source electrode and the gate electrode, and a second polarization layer resides on the gallium nitride layer between the gate electrode and the drain electrode. The silicon substrate can include a silicon 111 substrate.

Silicon PMOS with gallium nitride NMOS for voltage regulation

Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface.

Methods of forming hetero-layers with reduced surface roughness and bulk defect density of non-native surfaces and the structures formed thereby

Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate.

Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition

An epitaxial wafer comprises a silicon substrate wafer having first and second sides, and a silicon epitaxial layer deposited on the first side, and optionally one or more additional epitaxial layers on top of the silicon epitaxial layer, at least one of the silicon epitaxial layer or at least one of the one or more additional epitaxial layers being doped with nitrogen at a concentration of 1&#xd7;10atoms/cmor more and 1&#xd7;10atoms/cmor less. The epitaxial wafer is produced by depositing the silicon epitaxial layer and/or at least one of the one or more additional epitaxial layers, at a deposition temperature of 940&#xb0; C. or less through chemical vapor deposition in the presence of a deposition gas atmosphere containing one or more silicon precursor compounds and one or more nitrogen precursor compounds.

Epitaxial wafer and a method of manufacturing thereof

A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1&#xd7;10cmto be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.

Stacking fault and twin blocking barrier for integrating III-V on Si

The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium ('Ge') transistor structure on a Silicon ('Si') substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

High hole mobility p-channel Ge transistor structure on Si substrate

Dislocation removal from a group III-V film grown on a semiconductor substrate is generally described. In one example, an apparatus includes a semiconductor substrate, a buffer film including a group III-V semiconductor material epitaxially coupled to the semiconductor substrate wherein the buffer film includes material melted by laser pulse irradiation and recrystallized to substantially remove dislocations or defects from the buffer film, and a first semiconductor film epitaxially grown on the buffer film wherein a lattice mismatch exists between the semiconductor substrate and the first semiconductor film.

Dislocation removal from a group III-V film grown on a semiconductor substrate

Various embodiments provide a buffer layer that is grown over a silicon substrate that provides desirable device isolation for devices formed relative to III-V material device layers, such as InSb-based devices, as well as bulk thin film grown on a silicon substrate. In addition, the buffer layer can mitigate parallel conduction issues between transistor devices and the silicon substrate. In addition, the buffer layer addresses and mitigates lattice mismatches between the film relative to which the transistor is formed and the silicon substrate.

Buffer layers for device isolation of devices grown on silicon

Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a GaSb nucleation layer on a substrate, forming a Ga(Al)AsSb buffer layer on the GaSb nucleation layer, forming an InAlAs bottom barrier layer on the Ga(Al)AsSb buffer layer, and forming a graded InAlAs layer on the InAlAs bottom barrier layer thus enabling the fabrication of low defect, device grade InGaAs based quantum well structures.

Methods of forming buffer layer architecture on silicon and structures formed thereby

A multi-layered substrate with bulk substrate characteristics and processes for the fabrication of such substrates are herein disclosed. The multi-layered substrate can include a first layer, a second layer and an interfacial layer therebetween. The first and second layers can be silicon, germanium, or any other suitable material of the same or different crystal orientations. The interfacial layer can be an oxide layer from about 5 Angstroms to about 50 Angstroms.

Ultra-thin oxide bonding for S1 to S1 dual orientation bonding

Growing community of inventors

Beaverton, OR, United States of America

Peter G Tolchinsky