The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2017

Filed:

Dec. 28, 2011
Applicants:

Niloy Mukherjee, Beaverton, OR (US);

Matthew V. Metz, Portland, OR (US);

James M. Powers, Beaverton, OR (US);

Van H. Le, Portland, OR (US);

Benjamin Chu-kung, Hillsboro, OR (US);

Mark R. Lemay, Vernonia, OR (US);

Marko Radosavljevic, Beaverton, OR (US);

Niti Goel, Hillsboro, OR (US);

Loren Chow, Los Altos, CA (US);

Peter G. Tolchinsky, Beaverton, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Robert S. Chau, Beaverton, OR (US);

Inventors:

Niloy Mukherjee, Beaverton, OR (US);

Matthew V. Metz, Portland, OR (US);

James M. Powers, Beaverton, OR (US);

Van H. Le, Portland, OR (US);

Benjamin Chu-Kung, Hillsboro, OR (US);

Mark R. Lemay, Vernonia, OR (US);

Marko Radosavljevic, Beaverton, OR (US);

Niti Goel, Hillsboro, OR (US);

Loren Chow, Los Altos, CA (US);

Peter G. Tolchinsky, Beaverton, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Robert S. Chau, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/06 (2013.01); H01L 21/0237 (2013.01); H01L 21/0245 (2013.01); H01L 21/0251 (2013.01); H01L 21/0259 (2013.01); H01L 21/02455 (2013.01); H01L 21/02494 (2013.01); H01L 21/02502 (2013.01); H01L 21/02505 (2013.01); H01L 21/02513 (2013.01); H01L 21/02532 (2013.01); H01L 21/02538 (2013.01); H01L 21/02587 (2013.01); H01L 21/02617 (2013.01); H01L 21/02636 (2013.01); H01L 21/02658 (2013.01); H01L 21/02664 (2013.01);
Abstract

Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface.


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