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For the Inventor, By the Inventor

Albany, NY, United States of America

Mona Abdulkhaleg Ebrish

This inventor holds 16 USPTO granted patents. Top assignee: International Business Machines Corporation. Active years: 2017-2023.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Mona Abdulkhaleg Ebrish. Retrieved from https://idiyas.com/inventor/mona-abdulkhaleg-ebrish

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 16

% Patents Active = 50.0

Average Co-Inventor Count = 4.5

ph-index = 4

Forward Citations = 451(Granted Patents)


Company Filing History:

goldMedal16 out of 166,351 
 
International Business Machines Corporation
 patents

Years Active: 2017-2023

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16 patents (USPTO):Explore Patents
1. 11569442 - Dielectric retention and method of forming memory pillar (2023-01-31),
2. 11043494 - Structure and method for equal substrate to channel height between N and P fin-FETs (2021-06-22),
3. 11031250 - Semiconductor structures of more uniform thickness (2021-06-08),
4. 10818751 - Nanosheet transistor barrier for electrically isolating the substrate from the source or drain regions (2020-10-27),
5. 10811528 - Two step fin etch and reveal for VTFETs and high breakdown LDVTFETs (2020-10-20),
6. 10804106 - High temperature ultra-fast annealed soft mask for semiconductor devices (2020-10-13),
7. 10734523 - Nanosheet substrate to source/drain isolation (2020-08-04),
8. 10388789 - Reducing series resistance between source and/or drain regions and a channel region (2019-08-20),
9. 10381348 - Structure and method for equal substrate to channel height between N and P fin-FETs (2019-08-13),
10. 10361306 - High acceptor level doping in silicon germanium (2019-07-23),
11. 10361127 - Vertical transport FET with two or more gate lengths (2019-07-23),
12. 10319855 - Reducing series resistance between source and/or drain regions and a channel region (2019-06-11),
13. 10229910 - Separate N and P fin etching for reduced CMOS device leakage (2019-03-12),
14. 9799736 - High acceptor level doping in silicon germanium (2017-10-24),
15. 9711507 - Separate N and P fin etching for reduced CMOS device leakage (2017-07-18),

Title: Mona Abdulkhaleg Ebrish: Pioneering Innovator in the World of Technology

Introduction:

Mona Abdulkhaleg Ebrish, a trailblazer in the world of technology, has made significant contributions to the field of innovation. Her passion for pushing boundaries and striving for excellence has solidified her reputation as a pioneering inventor. Based in Albany, NY (US), Mona's work continues to inspire the next generation of inventors and shape the future of technological advancements.

Latest Patents:

Mona Abdulkhaleg Ebrish holds an impressive portfolio of 16 patents, showcasing her expertise in cutting-edge technology. Her latest patents include "Dielectric retention and method of forming memory pillar," which revolutionizes the manufacturing process of magnetic random access memory devices and "Structure and method for equal substrate to channel height between N and P fin-FETs," which enhances the fabrication of fin field effect transistors.

Career Highlights:

Mona's career is highlighted by her groundbreaking innovations at International Business Machines Corporation (IBM). Her work at IBM has not only garnered recognition within the industry but has also contributed significantly to the advancement of technology on a global scale.

Collaborations:

Throughout her career, Mona has collaborated with esteemed colleagues such as Indira P Seshadri and Leigh Anne H Clevenger. These collaborations have led to the development of groundbreaking technologies and have further cemented Mona's status as a leader in the field of innovation.

Conclusion:

Mona Abdulkhaleg Ebrish's relentless pursuit of excellence and passion for innovation have positioned her as a true trailblazer in the world of technology. Her significant contributions continue to shape the landscape of technological advancements and inspire future generations of inventors to push the boundaries of what is possible in the field of innovation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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