The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2017

Filed:

Jul. 20, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Mona Abdulkhaleg Ebrish, Albany, NY (US);

Oleg Gluschenkov, Tannersville, NY (US);

Shogo Mochizuki, Clifton Park, NY (US);

Alexander Reznicek, Troy, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/167 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 21/225 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/167 (2013.01); H01L 21/02381 (2013.01); H01L 21/02532 (2013.01); H01L 21/2254 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/785 (2013.01);
Abstract

A gallium-doped sacrificial epitaxial or polycrystalline germanium layer is formed on a silicon germanium substrate having a high percentage of germanium followed by annealing to diffuse the gallium into the silicon germanium substrate. The germanium layer is selectively removed to expose the surface of a gallium-doped silicon germanium region within the silicon germanium substrate. The process has application to the formation of electrically conductive regions within integrated circuits such as source/drain regions and junctions without the introduction of carbon into such regions.


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