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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10818751 B1

PDFFull Text
Date of Patent:
Oct. 27, 2020

Filed:

Mar. 01, 2019

Nanosheet transistor barrier for electrically isolating the substrate from the source or drain regions

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Mona A. Ebrish, Albany, NY (US);

Fee Li Lie, Albany, NY (US);

Nicolas Loubet, Guilderland, NY (US);

Gauri Karve, Cohoes, NY (US);

Indira Seshadri, Niskayuna, NY (US);

Lawrence A. Clevenger, Saratoga Springs, NY (US);

Leigh Anne H. Clevenger, Rhinebeck, NY (US);

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

Attorney:

Cantor Colburn LLP

Primary Examiner:

Laura M Menz

Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0642 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823468 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract

Embodiments of the invention are directed to a nanosheet field effect transistor (FET) device. A non-limiting example of the nanosheet FET device includes a stack of channel nanosheets over a substrate, along with a source or drain (S/D) trench in a predetermined region of the substrate. The predetermined region of the substrate includes a region over which a S/D region of the nanosheet FET is formed. The S/D region of the nanosheet FET is formed at ends of a bottommost one of the stack of channel nanosheets. An isolation barrier is formed in the S/D trench. The isolation barrier is configured to substantially prevent the S/D region from being electrically coupled to the substrate.

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