International Business Machines Corporation

Mona Abdulkhaleg Ebrish

Indira P Seshadri

Fee Li Lie

Gauri V Karve

Leigh Anne H Clevenger

Lawrence Alfred Clevenger

Oleg Gluschenkov

Nicole A Saulnier

Deepika Priyadarshini

Alexander Reznicek

Shogo Mochizuki

Ekmini Anuja De Silva

Nicolas J Loubet

Michael Rizzolo

Isabel Cristina Chu

Brent A Anderson

Junli Wang

Theodorus E Standaert

Hemanth Jagannathan

Son Van Nguyen

Huiming Bu

Xuefeng Liu

Donald Francis Canaperi

Raghuveer Reddy Patlolla

Saba Zare

A method of manufacturing a magnetic random access memory device includes depositing a liner on an intermediate device including an opening in a sacrificial dielectric layer, depositing a conductive metal over the liner and in the opening, removing a portion of the conductive metal while preserving the liner and a thickness of the sacrificial dielectric layer, removing a first portion of the liner by etching, wherein the liner is recessed into the opening, depositing a plurality of metallic tunnel junction layers, forming a hardmask on the plurality of metallic tunnel junction layers, and patterning the metallic tunnel junction layers to form a metallic tunnel junction stack and simultaneously clear a second portion of the liner and a portion the sacrificial dielectric layer.

Dielectric retention and method of forming memory pillar

A method for fabricating fin field effect transistors comprises creating a pattern of self-aligned small cavities for P-type material growth using at least two hard mask layers, generating a pre-defined isolation area around each small cavity using a vertical spacer, selectively removing N-type material from the self-aligned small cavities, and growing P-type material in the small cavities. The P-type material may be silicon germanium (SiGe) and the N-type material may be tensile Silicon (t-Si). The pattern of self-aligned small cavities for P-type material growth is created by depositing two hard mask materials over a starting substrate wafer, selectively depositing photo resist over a plurality N-type areas, reactive ion etching to remove the second hard mask layer material over areas not covered by photo resist to create gaps in second hard mask layer, and removing the photo resist to expose the second hard mask material in the N-type areas.

Structure and method for equal substrate to channel height between N and P fin-FETs

A semiconductor device and method of formation thereof. The semiconductor device includes a portion of a first material that abuts a portion of a second material and surrounds at least a portion of a semiconductor component. The first material has a first composition and a first index of refraction and is of a same type of material as the second material. The second material has a second composition and a second index of refraction. An opening in the first material exposes a portion of the semiconductor component.

Semiconductor structures of more uniform thickness

Embodiments of the invention are directed to a nanosheet field effect transistor (FET) device. A non-limiting example of the nanosheet FET device includes a stack of channel nanosheets over a substrate, along with a source or drain (S/D) trench in a predetermined region of the substrate. The predetermined region of the substrate includes a region over which a S/D region of the nanosheet FET is formed. The S/D region of the nanosheet FET is formed at ends of a bottommost one of the stack of channel nanosheets. An isolation barrier is formed in the S/D trench. The isolation barrier is configured to substantially prevent the S/D region from being electrically coupled to the substrate.

Nanosheet transistor barrier for electrically isolating the substrate from the source or drain regions

High breakdown voltage devices are provided. In one aspect, a method of forming a device having a VTFET and a LDVTFET includes: forming a LDD in an LDVTFET region; patterning fin(s) in a VTFET region to a depth D1; patterning fin(s) in the LDVTFET region, through the LDD, to a depth D2&#x3e;D1; forming bottom source/drains at a base of the VTFET/LDVTFET fins; burying the VTFET/LDVTFET fins in a gap fill dielectric; recessing the gap fill dielectric to full expose the VTFET fin(s) and partially expose the LDVTFET fin(s); forming bottom spacers directly on the bottom source/drains in the VTFET region and directly on the gap fill dielectric in the LDVTFET region; forming gates alongside the VTFET/LDVTFET fins; forming top spacers above the gates; and forming top source/drains above the top spacers. A one-step fin etch and devices having VTFET and long channel VTFETs are also provided.

Two step fin etch and reveal for VTFETs and high breakdown LDVTFETs

Techniques for providing a high temperature soft mask for semiconductor devices are described. In an embodiment, spin coating semiconductor device components with organic planarization material having a defined aromatic content aromatic content to provide an organic planarization layer. The method can further comprise ultra-fast annealing the organic planarization layer and forming an implanted or doped region in the semiconductor device. Three-dimensional FinFET components of a device can be spin coated with organic planarization material having high aromatic content, with the device cured at a first temperature. The organic planarization layer can be ultra-fast annealed at a second temperature that is greater than the first temperature. Aspects can include patterning the device, and forming an implanted or doped region in a semiconductor device.

High temperature ultra-fast annealed soft mask for semiconductor devices

A method of forming a nanosheet device is provided. The method includes forming a nanosheet channel layer stack and dummy gate structure on a substrate. The method further includes forming a curved recess in the substrate surface adjacent to the nanosheet channel layer stack. The method further includes depositing a protective layer on the curved recess, dummy gate structure, and exposed sidewall surfaces of the nanosheet layer stack, and removing a portion of the protective layer on the curved recess to form a downward-spiked ridge around the rim of the curved recess. The method further includes extending the curved recess deeper into the substrate to form an extended recess, and forming a sacrificial layer at the surface of the extended recess in the substrate.

Nanosheet substrate to source/drain isolation

A method for reducing series resistance for transistors includes forming a conductive gate over and insulated from a semiconductor substrate, forming source and/or drain extension regions within the substrate and adjacent to respective source and/or drain regions, and forming source and/or drain regions within the substrate. The source and/or drain extension regions are formed from a material alloyed with a first dopant and a second dopant, the first dopant configured to increase a lattice structure of the material forming the source and/or drain extension regions.

Reducing series resistance between source and/or drain regions and a channel region

A semiconductor structure is provided in which gallium-doped sacrificial epitaxial or polycrystalline germanium layer is formed on a silicon germanium substrate having a high percentage of germanium followed by annealing to diffuse the gallium into the silicon germanium substrate. The germanium layer is selectively removed to expose the surface of a gallium-doped silicon germanium region within the silicon germanium substrate. The process has application to the formation of electrically conductive regions within integrated circuits such as source/drain regions and junctions without the introduction of carbon into such regions.

High acceptor level doping in silicon germanium

A method for forming a device with multiple gate lengths includes forming a gate stack on vertical fins. A cutting mask formed on the gate stack is etched to include two or more different heights. Gate structures with two or more gate lengths are etched by employing the two or more different heights in the cutting mask as an etch mask. The cutting mask is removed. A top source/drain regions is formed on top of the vertical fins.

Vertical transport FET with two or more gate lengths

A method for forming a semiconductor device includes blocking a first region of a wafer and forming a plurality of fins in a second region of the wafer. A protective conformal mask layer is deposited over the plurality of fins in the second region, the second region is blocked, and a plurality of fins are formed in the first region of the wafer using a variety of wet and/or dry etching procedures. The protective conformal mask layer protects the plurality of fins in the second region from the variety of wet and/or dry etching procedures that are used to form the plurality of fins in the first region.

Separate N and P fin etching for reduced CMOS device leakage

A gallium-doped sacrificial epitaxial or polycrystalline germanium layer is formed on a silicon germanium substrate having a high percentage of germanium followed by annealing to diffuse the gallium into the silicon germanium substrate. The germanium layer is selectively removed to expose the surface of a gallium-doped silicon germanium region within the silicon germanium substrate. The process has application to the formation of electrically conductive regions within integrated circuits such as source/drain regions and junctions without the introduction of carbon into such regions.

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Albany, NY, United States of America

Mona Abdulkhaleg Ebrish