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For the Inventor, By the Inventor

Poughkeepsie, NY, United States of America

Kejia Wang

This inventor holds 23 USPTO granted patents and 3 published patent applications, primarily in Semiconductor Devices. Top assignees: International Business Machines Corporation, Globalfoundries Inc., Stmicroelectronics Gmbh. Active years: 2012-2019.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kejia Wang. Retrieved from https://idiyas.com/inventor/kejia-wang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 23 

% Patents Active = 47.8

Average Co-Inventor Count = 4.5

ph-index = 7

Forward Citations = 437(Granted Patents)


Location History:

  • Yorktown Heights, NY (US) (2012)
  • Fishkill, NY (US) (2013 - 2016)
  • Poughkeepsie, NY (US) (2013 - 2018)
  • Harrison, NY (US) (2018 - 2019)

Company Filing History:

goldMedal20 out of 166,351 
 
International Business Machines Corporation
 patents
silverMedal14 out of 5,671 
 
Globalfoundries Inc.
 patents
bronzeMedal11 out of 2,891 
 
Stmicroelectronics Gmbh
 patents
where one patent can have more than one assignee

Years Active: 2012-2019

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Areas of Expertise:
III-V Semiconductors
Field Effect Transistors
FinFETs
Photovoltaic Devices
Atomic Layer Deposition
Solar Cells
Epitaxial Growth
Nanowire Fabrication
Kesterite
Thin Films
Light Trapping
Nodules Avoidance
23 patents (USPTO):Explore Patents
1. 10355086 - High doped III-V source/drain junctions for field effect transistors (2019-07-16),
2. 10256304 - High doped III-V source/drain junctions for field effect transistors (2019-04-09),
3. 9935201 - High doped III-V source/drain junctions for field effect transistors (2018-04-03),
4. 9935179 - Method for making semiconductor device with filled gate line end recesses (2018-04-03),
5. 9917195 - High doped III-V source/drain junctions for field effect transistors (2018-03-13),
6. 9660057 - Method of forming a reduced resistance fin structure (2017-05-23),
7. 9653579 - Method for making semiconductor device with filled gate line end recesses (2017-05-16),
8. 9620505 - Semiconductor device with different fin sets (2017-04-11),
9. 9437677 - Deposition on a nanowire using atomic layer deposition (2016-09-06),
10. 9318579 - Method for making a semiconductor device while avoiding nodules on a gate (2016-04-19),
11. 9299775 - Methods for the production of integrated circuits comprising epitaxially grown replacement structures (2016-03-29),
12. 9299721 - Method for making semiconductor device with different fin sets (2016-03-29),
13. 9275861 - Methods of forming group III-V semiconductor materials on group IV substrates and the resulting substrate structures (2016-03-01),
14. 9202919 - FinFETs and techniques for controlling source and drain junction profiles in finFETs (2015-12-01),
15. 9041141 - Structure and method of fabricating a CZTS photovoltaic device by electrodeposition (2015-05-26),

Title: Kejia Wang: Innovating the Semiconductor Industry in Poughkeepsie

Introduction:

In the vibrant realm of semiconductor technology stands Kejia Wang, a prolific inventor based in Poughkeepsie, NY. With a remarkable portfolio of 23 patents, Wang is revolutionizing the field with his cutting-edge innovations.

Latest Patents:

Wang's latest patents showcase his expertise in semiconductor device design, particularly focusing on high doped III-V source/drain junctions for field-effect transistors. These patents highlight a semiconductor device with a unique fin pattern, epitaxial contacts, and a channel region comprising doped III-V materials. The intricate designs reflect Wang's dedication to pushing the boundaries of semiconductor engineering.

Career Highlights:

Having made significant contributions to the industry, Wang has honed his skills at prominent companies such as IBM and Globalfoundries Inc. His tenure at these renowned organizations has been marked by groundbreaking research and development in semiconductor technology, solidifying his reputation as a trailblazer in the field.

Collaborations:

Throughout his career, Wang has collaborated closely with esteemed colleagues, including Qing Liu and Ruilong Xie. These partnerships have been instrumental in driving innovation and fostering a culture of excellence in semiconductor research and development.

Conclusion:

In conclusion, Kejia Wang's exceptional work in the semiconductor industry exemplifies the spirit of innovation and ingenuity. His impressive patent portfolio, coupled with his extensive collaborations and industry experience, cements his legacy as a visionary inventor shaping the future of semiconductor technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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