International Business Machines Corporation

Globalfoundries Inc.

Stmicroelectronics Gmbh

Kejia Wang

Ruilong Xie

Chun-chen Yeh

Qing Liu

Xiuyu Cai

Supratik Guha

Dechao Guo

Hariklia Deligianni

Zhen Zhang

Zhengwen O Li

Lubomyr Taras Romankiw

Shafaat Ahmed

Ying Di Zhang

Daniel Chanemougame

Oki Gunawan

Yu Zhu

George Stojan Tulevski

Shurong Liang

William S Graham

Bin Yang

Teodor Krassimirov Todorov

Steven J Bentley

David Brian Mitzi

Li Ping Yang

Sylvie M Mignot

Ashish Baraskar

A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1eto about 1eatoms/cmand contacting the epitaxial contacts.

High doped III-V source/drain junctions for field effect transistors

A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1eto about 1eatoms/cmand contacting the epitaxial contacts.

A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.

Method for making semiconductor device with filled gate line end recesses

Methods and structures for forming a reduced resistance region of a finFET are described. According to some aspects, a dummy gate and first gate spacer may be formed above a fin comprising a first semiconductor composition. At least a portion of source and drain regions of the fin may be removed, and a second semiconductor composition may be formed in the source and drain regions in contact with the first semiconductor composition. A second gate spacer may be formed covering the first gate spacer. The methods may be used to form finFETs having reduced resistance at source and drain junctions.

Method of forming a reduced resistance fin structure

A semiconductor device which includes: a substrate; a first set of fins above the substrate of a first semiconductor material; a second set of fins above the substrate and of a second semiconductor material different than the first semiconductor material; and an isolation region positioned between the first and second sets of fins, the isolation region having a nitride layer. The isolation region may be an isolation pillar or an isolation trench.

Semiconductor device with different fin sets

A semiconductor device includes a substrate, a nanowire, a first structure, and a second structure. The nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate, where the nanowire includes a layer on a surface of the nanowire, where the layer includes at least one of silicide and carbide, where the layer has a substantially uniform shape.

Deposition on a nanowire using atomic layer deposition

A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate, and a gate overlying the semiconductor fins. The gate has a tapered outer surface. A first pair of sidewall spacers is formed adjacent the gate an exposed tapered outer surface is also defined. Portions of the gate are removed at the exposed tapered outer surface to define a recess. A second pair of sidewall spacers is formed covering the first pair of sidewall spacers and the recess. Source/drain regions are formed on the semiconductor fins.

Method for making a semiconductor device while avoiding nodules on a gate

A method for making a semiconductor device may include forming, above a substrate, first and second semiconductor regions laterally adjacent one another and each including a first semiconductor material. The first semiconductor region may have a greater vertical thickness than the second semiconductor region and define a sidewall with the second semiconductor region. The method may further include forming a spacer above the second semiconductor region and adjacent the sidewall, and forming a third semiconductor region above the second semiconductor region and adjacent the spacer, with the second semiconductor region including a second semiconductor material different than the first semiconductor material. The method may also include removing the spacer and portions of the first semiconductor material beneath the spacer, forming a first set of fins from the first semiconductor region, and forming a second set of fins from the second and third semiconductor regions.

Method for making semiconductor device with different fin sets

Integrated circuits and methods for producing such integrated circuits are provided. A method for producing the integrated circuit includes forming dummy structures in a substrate, and forming shallow trench isolation regions between the dummy structures where the shallow trench isolation regions includes a liner overlying a core. The dummy structures are etched to expose structure bases, and the structure bases are precleaned. Replacement structures are epitaxially grown over the structure bases.

Methods for the production of integrated circuits comprising epitaxially grown replacement structures

One method disclosed herein includes forming a patterned mask layer above a surface of a semiconductor substrate, performing at least one etching process through the patterned mask layer to define a plurality of intersecting ridges that define a ridged surface in the substrate, and forming a Group III-V material on the ridged surface of the substrate. An illustrative device disclosed herein includes a Group IV substrate having a ridged surface comprised of a plurality of intersecting ridges and a Group III-V material layer positioned on the ridged surface of the Group IV substrate.

Methods of forming group III-V semiconductor materials on group IV substrates and the resulting substrate structures

Techniques and structures for shaping the source and drain junction profiles of a finFET are described. A fin may be partially recessed at the source and drain regions of the finFET. The partially recessed fin may be further recessed laterally and vertically, such that the laterally recessed portion extends under at least a portion of the finFET's gate structure. Source and drain regions of the finFET may be formed by growing a buffer layer on the etched surfaces of the fin and/or growing a source and drain layer at the source and drain regions of the fin. The lateral recess can improve channel-length uniformity along the height of the fin.

FinFETs and techniques for controlling source and drain junction profiles in finFETs

Techniques for using electrodeposition to form absorber layers in diodes (e.g., solar cells) are provided. In one aspect, a method for fabricating a diode is provided. The method includes the following steps. A substrate is provided. A backside electrode is formed on the substrate. One or more layers are electrodeposited on the backside electrode, wherein at least one of the layers comprises copper, at least one of the layers comprises zinc and at least one of the layers comprises tin. The layers are annealed in an environment containing a sulfur source to form a p-type CZTS absorber layer on the backside electrode. An n-type semiconductor layer is formed on the CZTS absorber layer. A transparent conductive layer is formed on the n-type semiconductor layer. A diode is also provided.

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Poughkeepsie, NY, United States of America

Kejia Wang