The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2016

Filed:

May. 19, 2014
Applicants:

Stmicroelectronics, Inc, Coppell, TX (US);

Globalfoundries Inc., Grand Cayman, KY;

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Qing Liu, Watervliet, NY (US);

Xiuyu Cai, Niskayuna, NY (US);

Ruilong Xie, Schenectady, NY (US);

Chun-chen Yeh, Clifton Park, NY (US);

Kejia Wang, Poughkeepsie, NY (US);

Daniel Chanemougame, Grenoble, FR;

Assignees:

STMICROELECTRONICS, INC., Coppell, TX (US);

GLOBALFOUNDRIES INC, Grand Cayman, KY;

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/30 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1211 (2013.01); H01L 29/66795 (2013.01);
Abstract

A method for making a semiconductor device may include forming, above a substrate, first and second semiconductor regions laterally adjacent one another and each including a first semiconductor material. The first semiconductor region may have a greater vertical thickness than the second semiconductor region and define a sidewall with the second semiconductor region. The method may further include forming a spacer above the second semiconductor region and adjacent the sidewall, and forming a third semiconductor region above the second semiconductor region and adjacent the spacer, with the second semiconductor region including a second semiconductor material different than the first semiconductor material. The method may also include removing the spacer and portions of the first semiconductor material beneath the spacer, forming a first set of fins from the first semiconductor region, and forming a second set of fins from the second and third semiconductor regions.


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