The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2016

Filed:

Jun. 10, 2014
Applicants:

Stmicroelectronics, Inc., Coppell, TX (US);

Globalfoundries Inc., Grand Cayman, KY;

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Qing Liu, Watervliet, NY (US);

Ruilong Xie, Schenectady, NY (US);

Xiuyu Cai, Niskayuna, NY (US);

Kejia Wang, Poughkeepsie, NY (US);

Chun-chen Yeh, Clifton Park, NY (US);

Assignees:

STMICROELECTRONICS, INC., Coppell, TX (US);

GLOBALFOUNDRIES INC, Grand Cayman, KY;

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/28114 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01); H01L 29/7848 (2013.01);
Abstract

A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate, and a gate overlying the semiconductor fins. The gate has a tapered outer surface. A first pair of sidewall spacers is formed adjacent the gate an exposed tapered outer surface is also defined. Portions of the gate are removed at the exposed tapered outer surface to define a recess. A second pair of sidewall spacers is formed covering the first pair of sidewall spacers and the recess. Source/drain regions are formed on the semiconductor fins.


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