The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

May. 19, 2014
Applicants:

Stmicroelectronics, Inc., Coppell, TX (US);

Globalfoundries Inc, Grand Cayman, KY;

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Qing Liu, Watervliet, NY (US);

Ruilong Xie, Schenectady, NY (US);

Xiuyu Cai, Niskayuna, NY (US);

Chun-chen Yeh, Clifton Park, NY (US);

Kejia Wang, Poughkeepsie, NY (US);

Assignees:

STMicroelectronics, Inc., Coppell, TX (US);

GLOBALFOUNDRIES Inc, Grand Cayman, KY;

International Business Machines Corporation, Armonk, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 29/66545 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 27/0886 (2013.01); H01L 29/41791 (2013.01);
Abstract

A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.


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