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For the Inventor, By the Inventor

Wuhan, China

Kaiwei Li

This inventor holds 16 USPTO granted patents and 5 published patent applications and 2 EPO patents. Top assignees: Yangtze Memory Technologies Co., Ltd., Yangtze Memory Technologies., Ltd.. Active years: 2021-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kaiwei Li. Retrieved from https://idiyas.com/inventor/kaiwei-li

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 16 

% Patents Active = 81.3

 

Average Co-Inventor Count = 6.7

ph-index = 2

Forward Citations = 13(Granted Patents)


Company Filing History:

goldMedal13 out of 1,190 
 
Yangtze Memory Technologies Co., Ltd.
 patents
silverMedal3 out of 305 
 
Yangtze Memory Technologies., Ltd.
 patents

Years Active: 2021-2026

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16 patents (USPTO):Explore Patents
1. 12763148 - Memory device and erasing and verification method thereof (2026-10-13),
2. 12700457 - Memory device and program operation thereof (2026-08-04),
3. 12633356 - Method and memory used for reducing program disturbance by adjusting voltage of dummy word line (2026-05-19),
4. 12412609 - Method of reducing program disturbance in memory device and memory device utilizing same (2025-09-09),
5. 12354668 - Programming method for semiconductor device and semiconductor device (2025-07-08),
6. 12100456 - Memory device and erasing and verification method thereof (2024-09-24),
7. 11848058 - Method and memory used for reducing program disturbance by adjusting voltage of dummy word line (2023-12-19),
8. 11676665 - Memory device and erasing and verification method thereof (2023-06-13),
9. 11676646 - Method of reducing program disturbance in memory device and memory device utilizing same (2023-06-13),
10. 11626170 - Method and memory used for reducing program disturbance by adjusting voltage of dummy word line (2023-04-11),
11. 11222674 - Method of sequentially biasing bias lines in memory device for program disturbance reduction and memory device utilizing same (2022-01-11),
12. 11205494 - Non-volatile memory device and control method (2021-12-21),
13. 11158380 - Memory device and erasing and verification method thereof (2021-10-26),
14. 10991438 - Method and memory used for reducing program disturbance by adjusting voltage of dummy word line (2021-04-27),
15. 10957408 - Non-volatile memory device and control method (2021-03-23),

Title: Innovations of Inventor Kaiwei Li

Introduction

Kaiwei Li is a prominent inventor based in Wuhan, China. He has made significant contributions to the field of memory devices, holding a total of 16 patents. His work focuses on enhancing the performance and efficiency of semiconductor technologies.

Latest Patents

Among his latest patents is a method of reducing program disturbance in memory devices. This invention includes a memory device with multiple memory strings and a peripheral circuit designed to maintain specific voltages during programming operations. Another notable patent involves a programming method for semiconductor devices, which outlines a systematic approach to applying voltages to memory cells to optimize programming efficiency.

Career Highlights

Kaiwei Li is currently employed at Yangtze Memory Technologies Co., Ltd. His innovative work has positioned him as a key figure in the development of advanced memory solutions. His patents reflect a deep understanding of semiconductor technology and its applications.

Collaborations

Some of his notable coworkers include Jianquan Jia and An Zhang. Their collaborative efforts contribute to the ongoing advancements in memory technology at their company.

Conclusion

Kaiwei Li's contributions to the field of memory devices through his patents and innovative methods highlight his expertise and commitment to advancing semiconductor technology. His work continues to influence the industry significantly.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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