Memory device and erasing and verification method thereof

Abstract

A memory device includes a memory string and a control circuit. The memory string includes a top select gate, a memory cell, and a bottom select gate. The top select gate is coupled to a first select line, the memory cell is coupled to a word line, and the bottom select gate is coupled to a second select line. The control circuit is coupled to the first select line, the word line, and the second select line. The control circuit is configured to, in an erasing operation comprising an erasing stage and a verification stage after the erasing stage, apply an erasing voltage to the memory string in the erasing stage, apply a first voltage to the word line in a first stage of the verification stage, apply a second voltage lower than the first voltage to the word line in a second stage after the first stage, apply a first turn-on voltage to the second select line before applying the second voltage to the word line, and apply a second turn-on voltage to the first select line after stopping application of the erasing voltage for a period of time.