The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Oct. 08, 2024
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Kaiwei Li, Wuhan, CN;

Kaikai You, Wuhan, CN;

Junbao Wang, Wuhan, CN;

Jianquan Jia, Wuhan, CN;

Wenhao Xiong, Wuhan, CN;

Xiangnan Zhao, Wuhan, CN;

Songmin Jiang, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01); H10B 43/10 (2023.02); H10B 43/35 (2023.02);
Abstract

In certain aspects, a memory device includes memory strings each including a first drain select gate (DSG) transistor, an insulating structure disposed between two adjacent sets of the memory strings and electrically separating the first DSG transistors of the two adjacent sets of the memory strings, first DSG line, each coupled to the first DSG transistors in a respective set of the two adjacent sets of the memory strings, and a peripheral circuit coupled to the memory strings through the first DSG lines and configured to, in an operation, apply a negative voltage to an unselect first DSG line of the first DSG lines, wherein the unselect first DSG line is coupled to the first DSG transistors in an unselect set of the two adjacent sets of the memory strings.


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