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For the Inventor, By the Inventor

Hopewell Junction, NY, United States of America

Ian D Melville

This inventor holds 35 USPTO granted patents and 5 published patent applications, primarily in Semiconductor Reliability. Top assignees: International Business Machines Corporation, Globalfoundries Singapore Pte. Ltd., Enesas Electronics Corporation. Active years: 2004-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ian D Melville. Retrieved from https://idiyas.com/inventor/ian-d-melville

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 35 

% Patents Active = 54.3

Average Co-Inventor Count = 4.3

ph-index = 6

Forward Citations = 112(Granted Patents)


Location History:

  • Hopewell Junction, NY (US) (2014)
  • Highland, NY (US) (2004 - 2021)

Company Filing History:

goldMedal33 out of 166,325 
 
International Business Machines Corporation
 patents
silverMedal3 out of 1,058 
 
Globalfoundries Singapore Pte. Ltd.
 patents
bronzeMedal1 out of 1 
 
Enesas Electronics Corporation
 patent
4. 1 out of 5,671 
 
Globalfoundries Inc.
 patents
5. 1 out of 7,651 
 
Renesas Electronics Corporation
 patents
where one patent can have more than one assignee

Years Active: 2004-2021

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Areas of Expertise:
Bond Pad Reliability
Ionizing Radiation Blocking
Chip-to-Chip Interconnections
Stress-Resilient Structures
3D Integrated Circuits
Soft Error Mitigation
Electromigration Resistance
Crack Stop Regions
Thermo-Mechanical Stress
Passivation Layer Integrity
Solder Bump Support
Copper Plug Technology
35 patents (USPTO):Explore Patents
1. 10892239 - Bond pad reliability of semiconductor devices (2021-01-12),
2. 10784200 - Ionizing radiation blocking in IC chip to reduce soft errors (2020-09-22),
3. 10438894 - Chip-to-chip and chip-to-substrate interconnections in multi-chip semiconductor devices (2019-10-08),
4. 10211175 - Stress-resilient chip structure and dicing process (2019-02-19),
5. 9947645 - Multi-project wafer with IP protection by reticle mask pattern modification (2018-04-17),
6. 9431359 - Coaxial solder bump support structure (2016-08-30),
7. 9069923 - IP protection (2015-06-30),
8. 9059167 - Structure and method for making crack stop for 3D integrated circuits (2015-06-16),
9. 8999764 - Ionizing radiation blocking in IC chip to reduce soft errors (2015-04-07),
10. 8922019 - Semiconductor device having a copper plug (2014-12-30),
11. 8859390 - Structure and method for making crack stop for 3D integrated circuits (2014-10-14),
12. 8835289 - Wafer backside defectivity clean-up utilizing selective removal of substrate material (2014-09-16),
13. 8786059 - Passivation layer surface topography modifications for improved integrity in packaged assemblies (2014-07-22),
14. 8749059 - Semiconductor device having a copper plug (2014-06-10),
15. 8741769 - Semiconductor device having a copper plug (2014-06-03),

Title: The Inventor Ian D Melville: Pioneering Innovations in Hopewell Junction

Introduction: Ian D Melville is a distinguished inventor based in Hopewell Junction, NY, known for his groundbreaking contributions to various technological fields.

Latest Patents: Ian D Melville holds several patents in the areas of renewable energy technologies, advanced materials, and artificial intelligence systems, showcasing his versatility and forward-thinking approach.

Career Highlights: With a career spanning over two decades, Ian D Melville has worked with leading research institutions and tech companies to develop cutting-edge solutions that have revolutionized industries worldwide.

Collaborations: Throughout his career, Ian D Melville has collaborated with top engineers, scientists, and designers, fostering a culture of innovation and excellence in all his projects.

Conclusion: Ian D Melville's passion for innovation and his relentless pursuit of technological advancement continue to inspire the next generation of inventors and shape the future of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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