The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2019
Filed:
May. 30, 2018
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
Mukta Farooq, Hopewell Jct, NY (US);
Koushik Ramachandran, Wappigners Falls, NY (US);
Eric Perfecto, Poughkeepsie, NY (US);
Ian Melville, Highland, NY (US);
Assignee:
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/538 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5381 (2013.01); H01L 23/49838 (2013.01); H01L 24/17 (2013.01); H01L 25/0652 (2013.01); H01L 2224/1703 (2013.01); H01L 2225/0652 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06572 (2013.01);
Abstract
A multi-chip semiconductor device with multi-level structure including a substrate with a top substrate surface, a cavity with a depth in the substrate, a first chip having a top first chip surface with a first chip height, optionally including a second chip having a top second chip surface with a second chip height, and a connecting passive chip bridging the first chip, the second chip and the substrate by solder bumps wherein the solder bumps enable the connecting passive chip to be level.