Hsinchu, Taiwan

Chun-Yen Lin

This inventor holds 23 USPTO granted patents and 38 published patent applications, primarily in Semiconductor Technology. Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.. Active years: 2019-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chun-Yen Lin. Retrieved from https://idiyas.com/inventor/chun-yen-lin

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 23 

% Patents Active = 100.0

Average Co-Inventor Count = 3.6

ph-index = 3

Forward Citations = 15(Granted Patents)


Company Filing History:


Years Active: 2019-2026

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Areas of Expertise:
Semiconductor Device
Integrated Circuit
Leakage Reduction
CFET
Transistor Contacts
Standard Cell Design
Manufacturing Method
Pattern Layout
CMOS Architecture
Routing Flexibility
Active Regions
Mask Structure
23 patents (USPTO):Explore Patents

Title: Innovations of Chun-Yen Lin

Introduction

Chun-Yen Lin is a prominent inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of nine patents. His work focuses on methods and structures that enhance the efficiency and effectiveness of semiconductor manufacturing processes.

Latest Patents

Chun-Yen Lin's latest patents include innovative methods for forming pattern layouts and semiconductor structures. One of his notable patents describes a method for forming a pattern layout, which involves receiving an integrated circuit (IC) design layout that includes a layout block. This method outlines the formation of a first line pattern within the layout block and a second line pattern outside the block, ensuring they are parallel. Additionally, it details the creation of a mandrel bar pattern that overlaps both line patterns, facilitating the output of a precise pattern layout.

Another significant patent focuses on standard cell design with dummy padding. This semiconductor structure comprises a substrate with active regions and dummy regions strategically placed between them. The design ensures that the outer boundary line of the active and dummy regions includes at least two substantially 90-degree bends, optimizing the layout for better performance.

Career Highlights

Chun-Yen Lin is currently associated with Taiwan Semiconductor Manufacturing Company Limited, a leading firm in the semiconductor industry. His expertise and innovative approaches have contributed to advancements in semiconductor design and manufacturing.

Collaborations

Chun-Yen Lin has collaborated with notable colleagues, including Tung-Heng Hsieh and Bao-Ru Young. Their combined efforts have led to significant developments in semiconductor technologies.

Conclusion

Chun-Yen Lin's contributions to semiconductor innovation through his patents and collaborations highlight his role as a key figure in the industry. His work continues to influence the future of semiconductor manufacturing and design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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