Taiwan Semiconductor Manufacturing Comp. Ltd.

Chun-Yen Lin

Tung-Heng Hsieh

Bao-Ru Young

Chia-Sheng Fan

Jiann-Tyng Tzeng

Wei-Cheng Lin

Yuan-Te Hou

Sheng-Hsiung Wang

Yen-Hung Lin

A method includes: forming a first channel structure through a first gate structure; forming a first source/drain structure coupled to the first channel structure at a first surface of the first gate structure; before the first source/drain structure is formed, forming a first isolation layer at a second surface of the first gate structure to isolate the first channel structure; and after the first source/drain structure is formed, forming a first insulation structure at a position of the first isolation layer. The first surface and the second surface are opposite to each other, and a size of the first insulation structure is equal to or larger than a size of the first source/drain structure.

Semiconductor device and manufacturing method thereof

A method for forming a pattern layout is provided, including receiving an IC design layout including a layout block, a first line pattern is disposed inside the layout block along the first direction; forming a second line pattern disposed outside the layout block parallel to the first line patterns; forming a mandrel bar pattern oriented along the second direction and overlapping the first line pattern and the second line pattern, the mandrel bar pattern is between the first edge and the third edge of the layout block that are parallel to the first direction, and a first end of the mandrel bar pattern is separated from the first edge and overlaps a first side edge of one of the first line pattern or the second line pattern closest to the first edge; and outputting a pattern layout.

Methods for forming pattern layout, mask, and semiconductor structure

A semiconductor structure includes a substrate; a first column of active regions over the substrate; a second column of active regions over the substrate; and a dummy padding disposed between the first and the second columns from a top view. The dummy padding includes multiple dummy regions. A first dummy region of the multiple dummy regions is disposed between a first active region in the first column of active regions and a second active region in the second column of active regions. An outer boundary line tracing an edge of the first active region, an edge of the first dummy region, and an edge of the second active region includes at least two substantially 90-degree bends from a top view. The first and the second active regions include a semiconductor material doped with a same dopant.

Standard cell design with dummy padding

In some embodiments, the present disclosure relates to a method that includes removing portions of a substrate to form a continuous fin protruding from an upper surface of the substrate. A doping process is performed to selectively increase a dopant concentration of a first portion of the continuous fin. A first gate electrode is formed over a second portion of the continuous fin, and a second gate electrode is formed over a third portion of the continuous fin. The first portion of the continuous fin is between the second and third portions of the continuous fin. A dummy gate electrode is formed over the first portion of the continuous fin. Upper portions of the continuous fin that are arranged between the first gate electrode, the second gate electrode, and the dummy gate electrode are removed, and source/drain regions are formed between the first, the second, and the dummy gate electrodes.

Leakage reduction between two transistor devices on a same continuous fin

A method includes receiving an integrated circuit (IC) design layout including a layout block, where the layout block including first line patterns disposed along a first direction, extending lengths of the first line patterns, connecting portions of the first line patterns disposed within a distance less than a preset value, forming second line patterns disposed outside the layout block parallel to the first line patterns, forming mandrel bar patterns overlapping edges of the layout block, where the mandrel bar patterns oriented along a second direction perpendicular to the first direction, and outputting a pattern layout for mask fabricating, where the pattern layout includes the layout block, the first and second line patterns, and the mandrel bar patterns.

Method and structure for mandrel patterning

In some embodiments, the present disclosure relates to a method that includes removing portions of a substrate to form a continuous fin over the substrate. Further, a doping process is performed to selectively increase a dopant concentration of a first portion of the continuous fin. A first gate electrode is formed over a second portion of the continuous fin, and a second gate electrode is formed over a third portion of the continuous fin. The first portion of the continuous fin is between the second portion and the third portion of the continuous fin. A dummy gate electrode is formed over the first portion of the continuous fin. Upper portions of the continuous fin that are arranged between the first gate electrode, the second gate electrode, and the dummy gate electrode are removed, and source/drain regions are formed between the first, the second, and the dummy gate electrodes.

A method and structure for mitigating leakage current in devices that include a continuous active region. In some embodiments, a threshold voltage at the cell boundary is increased by changing a photomask logic operation (LOP) to reverse a threshold voltage type at the cell boundary. Alternatively, in some cases, the threshold voltage at the cell boundary is increased by performing a threshold voltage implant (e.g., an ion implant) at the cell boundary, and into a dummy gate disposed at the cell boundary. Further, in some embodiments, the threshold voltage at the cell boundary is increased by use of a silicon germanium (SiGe) channel at the cell boundary. In some cases, the SiGe may be disposed within the substrate at the cell boundary and/or the SiGe may be part of the dummy gate disposed at the cell boundary.

Leakage reduction methods and structures thereof

In some embodiments, the present disclosure relates to a method that includes receiving an initial layout design for a circuit schematic. The initial layout design includes a first gate electrode, a second gate electrode, and a third gate electrode arranged over a continuous fin. A first source/drain region is arranged between the first gate electrode and dummy gate electrode, and a second source/drain region is arranged between the second gate electrode and the dummy gate electrode. The method further includes determining if at least one of the first or second source/drain regions corresponds to a drain in the circuit schematic, and modifying the initial layout design to increase a dummy threshold voltage associated with the dummy gate electrode when the at least one of the first or second source/drain regions corresponds to the drain in the circuit schematic to provide a modified layout design.

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Hsinchu, Taiwan

Chun-Yen Lin