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For the Inventor, By the Inventor

HSINCHU, Taiwan

Chao-chun Lu

This inventor holds 27 USPTO granted patents and 32 published patent applications, primarily in Semiconductor Packaging. Top assignees: Invention and Collaboration Laboratory Pte. Ltd., Etron Technology, Inc., Nd-Hi Technologies Lab,inc.. Active years: 2025-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chao-chun Lu. Retrieved from https://idiyas.com/inventor/chao-chun-lu-4jc8fp8t

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 27 

% Patents Active = 44.4

Average Co-Inventor Count = 1.5

ph-index = 1

Forward Citations = 8(Granted Patents)


Company Filing History:

goldMedal17 out of 55 
 
Invention and Collaboration Laboratory Pte. Ltd.
 patents
silverMedal15 out of 304 
 
Etron Technology, Inc.
 patents
bronzeMedal6 out of 9 
 
Nd-Hi Technologies Lab,inc.
 patents
where one patent can have more than one assignee

Years Active: 2025-2026

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Areas of Expertise:
Semiconductor Package
3D IC Structure
Heat Removal
Transistor Structure
CMOS SRAM
Interconnection
Probe Card System
High Bandwidth Memory
Monolithic Integration
Diamond Composite Wafer
Die Package
Scaling Platform
27 patents (USPTO):Explore Patents
1. 12764919 - Homogeneous/ heterogeneous integration system with high performance computing and high storage volume (2026-10-13),
2. 12751308 - Semiconductor package and semiconductor package assembly with edge side interconnection (2026-09-29),
3. 12751289 - Semiconductor package and semiconductor package assembly with edge interconnection and method of forming the same (2026-09-29),
4. 12745405 - 3D IC structure (2026-09-22),
5. 12721165 - Semiconductor circuit structure with direct die heat removal structure (2026-08-25),
6. 12713625 - 3D IC STRUCTURE (2026-08-18),
7. 12707968 - Heat removing layer surrounding a transistor (2026-08-11),
8. 12707668 - Planar MOSFET with light, regular and heavily doped regions (2026-08-11),
9. 12696803 - Die package including a semiconductor die having a cavity within which a passive component is positioned, IC package and manufacturing process thereof (2026-07-28),
10. 12696494 - Method for forming transistor structure with a vertically grown source and drain (2026-07-28),
11. 12694926 - CMOS SRAM structure with bulk NMOS transistors and fully insulated PMOS transistors in one bulk wafer (2026-07-28),
12. 12666629 - 3D IC structure (2026-06-23),
13. 12660619 - Semiconductor device structure with efficient heat-removal structures across the chip and monolithic fabrication method therefor (2026-06-16),
14. 12633321 - Semiconductor device structure having a metal layer positioned under the semiconductor substrate (2026-05-19),
15. 12593688 - Manufacturing method of diamond composite wafer (2026-03-31),

Title: Innovator Spotlight: Chao-chun Lu

Introduction

Chao-chun Lu, based in Hsinchu, Taiwan, is a distinguished inventor recognized for his contributions to the field of semiconductor technologies. With a total of four patents to his name, Lu's work primarily focuses on advancements in semiconductor circuit structures, marking him as a notable figure in the innovation landscape.

Latest Patents

One of his latest innovations is the semiconductor circuit structure incorporating a direct die heat removal structure. This design features a semiconductor substrate with an original semiconductor surface and includes a set of active regions within the substrate. Notably, the structure employs a first shallow trench isolation (STI) region that borders the active regions. This first STI region comprises a heat removing layer, which is composed of material differing from silicon oxide (SiO), highlighting his emphasis on efficient thermal management in semiconductor devices.

Career Highlights

Chao-chun Lu has made significant strides in the tech industry, contributing to groundbreaking innovations in semiconductor technology. He has been instrumental in developing solutions that address common challenges in thermal efficiency, showcasing his commitment to advancing the capabilities of electronic components.

Collaborations

Throughout his career, Lu has collaborated with reputable organizations such as Invention and Collaboration Laboratory Pte. Ltd. and Etron Technology, Inc. His partnerships with these companies have fostered the development and commercialization of cutting-edge technologies, further enhancing his impact in the semiconductor sector.

Conclusion

Chao-chun Lu's inventive spirit and expertise in semiconductor technologies continue to make lasting impressions in the industry. His advancements in circuit structures emphasize the critical importance of innovation in achieving efficient and effective electronic solutions. As he progresses in his career, Lu's contributions are sure to inspire future breakthroughs in technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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