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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12696494 B1

PDFFull Text
Date of Patent:
Jul. 28, 2026

Filed:

Jul. 20, 2022

Method for forming transistor structure with a vertically grown source and drain

Applicant:

Invention and Collaboration Laboratory Pte. Ltd., Singapore, SG;

Inventors:

Chao-Chun Lu, Hsinchu, TW;

Li-Ping Huang, Hsinchu, TW;

Ming-Hong Kuo, Hsinchu, TW;

Assignee:

INVENTION AND COLLABORATION LABORATORY PTE. LTD., Singapore, SG;

Attorney:

McClure, Qualey & Rodack, LLP

Primary Examiner:

Nelson Garces

Int. Cl.
CPC ...
H10B 12/00 (2023.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 30/63 (2025.01);
U.S. Cl.
CPC ...
H10D 62/102 (2025.01); H10B 12/053 (2023.02); H10B 12/488 (2023.02); H10D 30/6715 (2025.01); H10D 30/6757 (2025.01); H10D 64/01 (2025.01); H10D 64/512 (2025.01); H10D 30/637 (2025.01); H10D 64/513 (2025.01);
Abstract

A method for forming a transistor structure includes steps as follows: A substrate with an original surface is prepared. Next a gate conductive region is formed, wherein at least a portion of the gate conductive region is disposed below the original surface, and a bottom wall and sidewalls of the gate conductive region is surrounded by a gate dielectric layer. Then, a first conductive region is formed, wherein a bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.

Find Patent Forward Citations

Lu, Chao-Chun. (2026). Method for forming transistor structure with a vertically grown source and drain (U.S. Patent No. 12696494). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12696494

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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