The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2026
Filed:
Apr. 21, 2023
Invention and Collaboration Laboratory, Inc., Taipei City, TW;
Etron Technology, Inc., Hsinchu City, TW;
Chao-Chun Lu, Hsinchu, TW;
INVENTION AND COLLABORATION LABORATORY, INC., Taipei City, TW;
ETRON TECHNOLOGY, INC., Hsinchu City, TW;
Abstract
A CMOS SRAM structure includes a Bulk semiconductor substrate with a PMOS active region and an NMOS active region. A set of PMOS transistors are formed in the PMOS active region and a set of NMOS transistors are formed in the NMOS active region. A VDD contacting line is electrically coupled to the set of PMOS transistors, a VSS contacting line is electrically coupled to the set of NMOS transistors, a word line is electrically coupled to the set of NMOS transistors, a bit line is electrically coupled to the set of NMOS transistors, and a complementary bit line is electrically coupled to the set of NMOS transistors. Wherein either the PMOS active region or the NMOS active region is a SOI region which is fully isolated from a rest portion of the Bulk semiconductor substrate which does not include the PMOS active region and the NMOS active region.