The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2026

Filed:

Sep. 01, 2025
Applicants:

Nd-hi Technologies Lab, Inc., Taipei City, TW;

Etron Technology, Inc., Hsinchu, TW;

Inventors:

Ho-Ming Tong, Taipei City, TW;

Chao-Chun Lu, Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/68 (2026.01); H10P 72/70 (2026.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 70/67 (2026.01); H10W 90/00 (2026.01); H10W 70/05 (2026.01); H10W 70/09 (2026.01); H10W 72/00 (2026.01); H10W 90/10 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 70/688 (2026.01); H10P 72/74 (2026.01); H10W 70/611 (2026.01); H10W 70/657 (2026.01); H10W 90/00 (2026.01); H10P 72/7436 (2026.01); H10W 70/05 (2026.01); H10W 70/09 (2026.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 72/0198 (2026.01); H10W 72/834 (2026.01); H10W 90/10 (2026.01); H10W 90/20 (2026.01); H10W 90/297 (2026.01); H10W 90/724 (2026.01); H10W 90/732 (2026.01);
Abstract

A semiconductor package includes a plurality of integrated circuit (IC) structures. Each IC structure includes: a first body having a primary surface and a secondary surface, wherein the primary surface is greater than the secondary surface in area; and a primary redistribution layer (RDL) over the primary surface of the first body, with the primary RDL having an edge surface aligned or substantially aligned with the secondary surface of the first body. The semiconductor package further includes an edge RDL over the secondary surface of the first body of each IC structure and the edge surface of the primary RDL of each IC structure. The primary RDL is electrically connected to the edge RDL and the first body, and the edge RDL is electrically connected to the first body through the primary RDL.


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