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For the Inventor, By the Inventor

Boise, ID, United States of America

Bhaskar Srinivasan

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This inventor holds 75 USPTO granted patents and 13 published patent applications and 4 EPO patents, primarily in Integrated Circuits (CPC class H01L). Top assignees: Micron Technology Incorporated, Texas Instruments Corporation, Boise Technology, Inc.. Active years: 2010-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Bhaskar Srinivasan. Retrieved from https://idiyas.com/inventor/bhaskar-srinivasan

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 75 

% Patents Active = 89.3

 

Average Co-Inventor Count = 3.0

ph-index = 6

Forward Citations = 169(Granted Patents)

Forward Citations (Not Self Cited) = 135(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Boise, ID (US) (2010 - 2017)
  • Plano, TX (US) (2013 - 2017)
  • Allen, TX (US) (2015 - 2024)

Company Filing History:

goldMedal53 out of 39,222 
 
Micron Technology Incorporated
 patents
silverMedal21 out of 29,888 
 
Texas Instruments Corporation
 patents
bronzeMedal1 out of 2 
 
Boise Technology, Inc.
 patents

Years Active: 2010-2025

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Areas of Expertise:
Integrated Circuits
Dielectric Layers
Ferroelectric Materials
Resistive Memory Cells
Polysilicon Engineering
Metal Oxides
Memory Arrays
Capacitors
Semiconductor Devices
Trench Capacitors
Analog Capacitors
Non-Volatile Memory
75 patents (USPTO):Explore Patents
1. 12512322 - Small grain size polysilicon engineering for threshold voltage mismatch improvement (2025-12-30),
2. 12424443 - Fin field-effect transistor semiconductor device and method of forming the same (2025-09-23),
3. 12406880 - Dielectric silicon nitride barrier deposition process for improved metal leakage and adhesion (2025-09-02),
4. 12170310 - Integrated circuits including composite dielectric layer (2024-12-17),
5. 12027515 - Carbon and/or oxygen doped polysilicon resistor (2024-07-02),
6. 12002846 - Integrated circuits having dielectric layers including an anti-reflective coating (2024-06-04),
7. 11849590 - Capacitor comprising a bismuth metal oxide-based lead titanate thin film (2023-12-19),
8. 11616011 - IC having trench-based metal-insulator-metal capacitor (2023-03-28),
9. 11605587 - Methods for etching metal interconnect layers (2023-03-14),
10. 11171200 - Integrated circuits having dielectric layers including an anti-reflective coating (2021-11-09),
11. 11158642 - Capacitor comprising a bismuth metal oxide-based lead titanate thin film (2021-10-26),
12. 11075157 - IC having trench-based metal-insulator-metal capacitor (2021-07-27),
13. 10680056 - IC with ion milled thin-film resistors (2020-06-09),
14. 10665663 - IC with top side capacitor having lateral regions with thinned capacitor dielectric (2020-05-26),
15. 10608075 - Analog capacitor on submicron pitch metal level (2020-03-31),

Title: The Innovative Journey of Inventor Bhaskar Srinivasan

Introduction:

Bhaskar Srinivasan, a talented inventor based in Boise, ID (US), has made significant contributions to the field of technology through his groundbreaking innovations.

Latest Patents:

Bhaskar Srinivasan holds several patents in the areas of artificial intelligence, renewable energy, and sustainable agriculture, showcasing his diverse range of expertise and interests.

Career Highlights:

With over two decades of experience in research and development, Bhaskar has worked for leading tech companies, where he spearheaded projects that have revolutionized the industry.

Collaborations:

Throughout his career, Bhaskar Srinivasan has collaborated with top researchers, engineers, and scientists from around the world, fostering a culture of innovation and knowledge sharing.

Conclusion:

Inventor Bhaskar Srinivasan's relentless pursuit of innovation and his passion for creating solutions to complex challenges make him a true visionary in the world of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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