The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Jan. 04, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Bhaskar Srinivasan, Allen, TX (US);

Guru Mathur, Plano, TX (US);

Stephen Arlon Meisner, Allen, TX (US);

Shih Chang Chang, Allen, TX (US);

Corinne Ann Gagnet, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 49/02 (2006.01); H01L 27/108 (2006.01); H01L 29/66 (2006.01); H01L 27/06 (2006.01); H01L 29/16 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 21/027 (2006.01); H01L 21/3213 (2006.01); H01L 23/532 (2006.01); H01L 23/522 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
H01L 28/40 (2013.01); H01L 21/022 (2013.01); H01L 21/0214 (2013.01); H01L 21/0276 (2013.01); H01L 21/02164 (2013.01); H01L 21/02211 (2013.01); H01L 21/02274 (2013.01); H01L 21/32139 (2013.01); H01L 21/76829 (2013.01); H01L 23/5223 (2013.01); H01L 23/53223 (2013.01); H01L 27/0629 (2013.01); H01L 27/10805 (2013.01); H01L 27/10808 (2013.01); H01L 29/1608 (2013.01); H01L 29/66181 (2013.01); H01L 29/94 (2013.01);
Abstract

An integrated circuit includes a capacitor located over a semiconductor substrate. The capacitor includes a first conductive layer having a first lateral perimeter, and a second conductive layer having a second smaller lateral perimeter. A first dielectric layer is located between the second conductive layer and the first conductive layer. The first dielectric layer has a thinner portion having the first lateral perimeter and a thicker portion having the second lateral perimeter. An interconnect line is located over the substrate, and includes a third conductive layer that is about coplanar with and has about a same thickness as the first conductive layer. A second dielectric layer is located over the third conductive layer. The second dielectric layer is about coplanar with and has about a same thickness as the thinner portion of the first dielectric layer.


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