The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2023

Filed:

Apr. 12, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Poornika Fernandes, Murphy, TX (US);

Bhaskar Srinivasan, Allen, TX (US);

Scott William Jessen, Allen, TX (US);

Guruvayurappan S. Mathur, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 49/02 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 21/0214 (2013.01); H01L 21/31111 (2013.01); H01L 21/32133 (2013.01); H01L 28/60 (2013.01);
Abstract

In some examples, a method comprises: obtaining a substrate having at a metal interconnect layer deposited over the substrate; forming a first dielectric layer on the metal interconnect layer; forming a second dielectric layer on the first dielectric layer; forming a capacitor metal layer on the second dielectric layer; patterning and etching the capacitor metal layer and the second dielectric layer to the first dielectric layer to leave a portion of the capacitor metal layer and the second dielectric layer on the first dielectric layer; forming an anti-reflective coating to cover the portion of the capacitor metal layer and the second dielectric layer, and to cover the metal interconnect layer; and patterning the metal interconnect layer to form a first metal layer and a second metal layer.


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