logo

For the Inventor, By the Inventor

Dresden, Germany

Andreas Gehring

This inventor holds 18 USPTO granted patents, primarily in Semiconductor Technology. Top assignees: Advanced Micro Devices Corporation, Globalfoundries Inc.. Active years: 2010-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Andreas Gehring. Retrieved from https://idiyas.com/inventor/andreas-gehring

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 18

% Patents Active = 61.1

Average Co-Inventor Count = 3.9

ph-index = 4

Forward Citations = 55(Granted Patents)


Company Filing History:

goldMedal10 out of 13,185 
 
Advanced Micro Devices Corporation
 patents
silverMedal8 out of 5,671 
 
Globalfoundries Inc.
 patents

Years Active: 2010-2014

Loading Chart...
Areas of Expertise:
Silicon-Germanium
Transistor
Strained Alloys
SOI Device
Capacitance Reduction
Embedded Alloys
Stress Memorization
Field Effect Transistor
18 patents (USPTO):Explore Patents
1. 8652913 - Method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss (2014-02-18),
2. 8530894 - Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions (2013-09-10),
3. 8377761 - SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device (2013-02-19),
4. 8298924 - Method for differential spacer removal by wet chemical etch process and device with differential spacer structure (2012-10-30),
5. 8227266 - Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions (2012-07-24),
6. 8183605 - Reducing transistor junction capacitance by recessing drain and source regions (2012-05-22),
7. 8129236 - Method for creating tensile strain by applying stress memorization techniques at close proximity to the gate electrode (2012-03-06),
8. 8093634 - In situ formed drain and source regions in a silicon/germanium containing transistor device (2012-01-10),
9. 7943442 - SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device (2011-05-17),
10. 7939399 - Semiconductor device having a strained semiconductor alloy concentration profile (2011-05-10),
11. 7897451 - Method for creating tensile strain by selectively applying stress memorization techniques to NMOS transistors (2011-03-01),
12. 7816199 - Method of forming a semiconductor structure comprising an implantation of ions of a non-doping element (2010-10-19),
13. 7790537 - Method for creating tensile strain by repeatedly applied stress memorization techniques (2010-09-07),
14. 7772077 - Method of forming a semiconductor structure comprising a field effect transistor having a stressed channel region (2010-08-10),
15. 7763505 - Method for reducing crystal defects in transistors with re-grown shallow junctions by appropriately selecting crystalline orientations (2010-07-27),

Title: The Innovative Contributions of Andreas Gehring

Introduction

Andreas Gehring is a prominent inventor based in Dresden, Germany. He has made significant contributions to the field of semiconductor technology, holding a total of 18 patents. His work focuses on enhancing the performance and efficiency of transistors, which are crucial components in modern electronic devices.

Latest Patents

One of his latest patents is a method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss. This innovation involves providing a protection layer on a silicon/germanium material of high germanium concentration, which significantly reduces or even completely avoids the loss of strained semiconductor material. The protection layer is formed prior to critical cleaning processes and is maintained until the formation of metal silicide regions. This advancement allows for high performance gain of P-type transistors without requiring massive overfill during the selective epitaxial growth process. Another notable patent is a test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions. This test structure evaluates the patterning process and/or the epitaxial growth process, enhancing statistical relevance while reducing test time.

Career Highlights

Throughout his career, Andreas Gehring has worked with leading companies in the semiconductor industry, including Advanced Micro Devices Corporation and Globalfoundries Inc. His expertise and innovative mindset have positioned him as a key player in the development of advanced semiconductor technologies.

Collaborations

Andreas has collaborated with notable professionals in the field, including Andy C Wei and Anthony Mowry. These collaborations have further enriched his work and contributed to the advancement of semiconductor technology.

Conclusion

Andreas Gehring's contributions to the semiconductor industry through his innovative patents and collaborations highlight his significant role in advancing technology. His work continues to influence the development of high-performance electronic devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…