The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8129236 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 06, 2012

Filed:

Oct. 24, 2008
Applicants:

Andreas Gehring, Dresden, DE;

Anthony Mowry, Buda, TX (US);

Andy Wei, Dresden, DE;

Inventors:

Andreas Gehring, Dresden, DE;

Anthony Mowry, Buda, TX (US);

Andy Wei, Dresden, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8249 (2006.01);
U.S. Cl.
CPC ...
Abstract

After forming the outer drain and source regions of an N-channel transistor, the spacer structure may be removed on the basis of an appropriately designed etch stop layer so that a rigid material layer may be positioned more closely to the gate electrode, thereby enhancing the overall strain-inducing mechanism during a subsequent anneal process in the presence of the material layer and providing an enhanced stress memorization technique (SMT). In some illustrative embodiments, a selective SMT approach may be provided.


Find Patent Forward Citations

Gehring, Andreas. (2012). Method for creating tensile strain by applying stress memorization techniques at close proximity to the gate electrode (U.S. Patent No. 8129236). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8129236

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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