The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 10, 2010
Filed:
May. 18, 2007
Andreas Gehring, Dresden, DE;
Andy Wei, Dresden, DE;
Anthony Mowry, Dresden, DE;
Manuj Rathor, Milpitas, CA (US);
Andreas Gehring, Dresden, DE;
Andy Wei, Dresden, DE;
Anthony Mowry, Dresden, DE;
Manuj Rathor, Milpitas, CA (US);
Advanced Micro Devices, Inc., Austin, TX (US);
Abstract
A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. The first transistor element comprises at least one first amorphous region and the second transistor element comprises at least one second amorphous region. A stress-creating layer is formed over the first transistor element. The stress-creating layer does not cover the second transistor element. A first annealing process is performed. The first annealing process is adapted to re-crystallize the first amorphous region and the second amorphous region. After the first annealing process, a second annealing process is performed. The stress-creating layer remains on the semiconductor substrate during the second annealing process.