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Singapore, Singapore

Sunedison Semiconductor Limited (uen201334164h)

USPTO Granted Patents = 38

Forward Citations = 177

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46 inventors (with patents filed for the assignee):

Jeffrey Louis Libbert (9 out of 53 patents)

Benno Orschel (6 out of 8 patents)

John Allen Pitney (6 out of 22 patents)

4. Michael R Seacrist (5 out of 21 patents)

5. Sumeet S Bhagavat (4 out of 31 patents)

6. Robert J Falster (4 out of 80 patents)

7. Peter D Albrecht (4 out of 24 patents)

8. Qingmin Liu (3 out of 22 patents)

9. Sasha Joseph Kweskin (3 out of 16 patents)

10. Mike Wolfram (3 out of 4 patents)

11. Vikas Berry (3 out of 11 patents)

12. Carissima Marie Hudson (2 out of 33 patents)

13. Shawn George Thomas (2 out of 43 patents)

14. Vladimir V Voronkov (2 out of 22 patents)

15. Henry Frank Erk (2 out of 30 patents)

Core Competencies:

Semiconductor On Insulator

Silicon Wafers

Epitaxial Reactor

Phase Shift Interferometry

Chemical Vapor Deposition

Graphene Formation

High Resistivity Wafers

Wafer Cleaving

Data Logging

Thermal Conductivity

Heterostructures

Monolayers

38 patents: Sort by Forward Citations

1. 10796946 - Method of manufacture of a semiconductor on insulator structure (2020-10-06),

2. 10707093 - Method of treating silicon wafers to have intrinsic gettering and gate oxide integrity yield (2020-07-07),

3. 10475696 - Method of manufacture of a semiconductor on insulator structure (2019-11-12),

4. 10453703 - Method of treating silicon wafers to have intrinsic gettering and gate oxide integrity yield (2019-10-22),

5. 10032659 - Methods and systems for preventing unsafe operations (2018-07-24),

6. 10030964 - Systems and methods for performing phase shift interferometry while a wafer is vibrating (2018-07-24),

7. 10026642 - Semiconductor on insulator structure comprising a sacrificial layer and method of manufacture thereof (2018-07-17),

8. 10007255 - Systems and methods for controlling temperatures in an epitaxial reactor (2018-06-26),

9. 9925755 - Clamping apparatus for cleaving a bonded wafer structure and methods for cleaving (2018-03-27),

10. 9899499 - High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss (2018-02-20),

11. 9881832 - Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof (2018-01-30),

12. 9853133 - Method of manufacturing high resistivity silicon-on-insulator substrate (2017-12-26),

13. 9831115 - Process flow for manufacturing semiconductor on insulator structures in parallel (2017-11-28),

14. 9768056 - Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition (2017-09-19),

15. 9727045 - Method and system for a meta-recipe control software architecture (2017-08-08),

Company Overview

Sunedison Semiconductor Limited is a leading provider of advanced semiconductor technologies, specializing in the development and manufacturing of silicon wafers for the global semiconductor industry. The company focuses on delivering high-performance materials that cater to various applications, including consumer electronics, automotive, and industrial sectors. With a strong emphasis on innovation, Sunedison Semiconductor is committed to enhancing the efficiency and capabilities of semiconductor devices, contributing to the evolution of technology across diverse markets.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 13 2026

38 Patents

#79 in Singapore

#79 in Singapore

#17,844 in the World

Singapore, Singapore

Sunedison Semiconductor Limited (uen201334164h)

Forward Citations = 177

46 inventors:

Jeffrey Louis Libbert (9 out of 53 patents)

Benno Orschel (6 out of 8 patents)

John Allen Pitney (6 out of 22 patents)

4. Michael R Seacrist (5 out of 21 patents)

5. Sumeet S Bhagavat (4 out of 31 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Sunedison Semiconductor Limited (uen201334164h). Retrieved from https://idiyas.com/company/sunedison-semiconductor-uen201334164h

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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