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London, United Kingdom

Robert J Falster

USPTO Granted Patents = 80 (Patent Applications = 2)

EPO Patents = 1

Average Co-Inventor Count = 2.2

ph-index = 15

Forward Citations = 633(Granted Patents)

Forward Citations (Not Self Cited) = 428(Dec 10, 2025)

Inventors with similar research interests:

Location History:

Oxford OX1 3PH, GB (1993)
Milan, IT (1993 - 2005)
Woodstock, GB (2019 - 2020)
London, GB (2001 - 2023)

Company Filing History:

Memc Electronic Materials, Inc.

Globalwafers Co., Ltd.

Sunedison Semiconductor Limited (uen201334164h)

Sunedison Semiconductor Ltd. (uen201334164h)

Sunedison, Inc.

Sunedison Semiconductor Limited

Memc Singapore Pte. Ltd. (uen200614794d)

8. 1 out of 832,843

Other

patents

Years Active: 1993-2023

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Areas of Expertise:

Silicon Wafers

Semiconductor Substrates

High Resistivity Silicon

Intrinsic Gettering

Oxygen Precipitation

Minority Carrier Lifetime

Single Crystal Silicon

Epitaxial Layers

Defect Density Control

Thermal Annealing

Heterostructures

Silicon-On-Insulator

80 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 11764071 - Apparatus for stressing semiconductor substrates (2023-09-19),

2. 11655560 - High resistivity single crystal silicon ingot and wafer having improved mechanical strength (2023-05-23),

3. 11655559 - High resistivity single crystal silicon ingot and wafer having improved mechanical strength (2023-05-23),

4. 11282715 - Apparatus for stressing semiconductor substrates (2022-03-22),

5. 11276583 - Apparatus for stressing semiconductor substrates (2022-03-15),

6. 11276582 - Apparatus for stressing semiconductor substrates (2022-03-15),

7. 11142844 - High resistivity single crystal silicon ingot and wafer having improved mechanical strength (2021-10-12),

8. 10707093 - Method of treating silicon wafers to have intrinsic gettering and gate oxide integrity yield (2020-07-07),

9. 10453703 - Method of treating silicon wafers to have intrinsic gettering and gate oxide integrity yield (2019-10-22),

10. 10361097 - Apparatus for stressing semiconductor substrates (2019-07-23),

11. 9634098 - Oxygen precipitation in heavily doped silicon wafers sliced from ingots grown by the Czochralski method (2017-04-25),

12. 9583364 - Processes and apparatus for preparing heterostructures with reduced strain by radial compression (2017-02-28),

13. 9583363 - Processes and apparatus for preparing heterostructures with reduced strain by radial distension (2017-02-28),

14. 9142616 - Silicon wafers with suppressed minority carrier lifetime degradation (2015-09-22),

15. 9129919 - Production of high precipitate density wafers by activation of inactive oxygen precipitate nuclei (2015-09-08),

Title: Robert J Falster - Pioneering Inventor from London, GB

Introduction: Robert J Falster is a distinguished inventor based in London, GB, known for his groundbreaking contributions to various fields through his innovative creations.

Latest Patents: Robert J Falster holds several patents in the areas of renewable energy technologies, sustainable materials, and advanced robotics, showcasing his commitment to driving progress through invention.

Career Highlights: With a career spanning over two decades, Robert J Falster has established himself as a visionary inventor with a keen focus on developing solutions that address pressing global challenges. His work has been recognized for its ingenuity and practicality.

Collaborations: Throughout his career, Robert J Falster has collaborated with leading research institutions, universities, and companies to bring his inventions to life. His partnerships have been instrumental in advancing his ideas from concept to reality.

Conclusion: Robert J Falster's passion for innovation and his relentless pursuit of excellence have solidified his reputation as a trailblazing inventor in London, GB, and beyond. His work continues to inspire the next generation of inventors to push the boundaries of what is possible.

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