Memc Electronic Materials, Inc.

Globalwafers Co., Ltd.

Sunedison Semiconductor Limited (uen201334164h)

Other

Sunedison, Inc.

Sunedison Semiconductor Limited

Memc Singapore Pte. Ltd. (uen200614794d)

Sunedison Semiconductor Ltd. (uen201334164h)

Robert J Falster

Vladimir V Voronkov

Massimiliano Olmo

Daniela Gambaro

Marco Cornara

Joseph C Holzer

Harold W Korb

Paolo Mutti

John Allen Pitney

Peter D Albrecht

Martin Jeffrey Binns

Carissima Marie Hudson

Jeffrey Louis Libbert

Igor Peidous

Soubir Basak

Bayard K Johnson

Lu Fei

HyungMin Lee

Steve A Markgraf

Seamus A McQuaid

Luciano Mule'Stagno

Gabriella Borionetti

ByungChun Kim

Mohsen Banan

Jae-Woo Ryu

Francesco Bonoli

Alan Wang

Luciano Mule&prime;Stagno

Young Jung Lee

Byung Chun Kim

Giancarlo Ferrero

Graham Fisher

Marco Pagani

Soon Sung Park

Tae Hoon Kim

Jun Hwan Ji

Steven Lawrence Kimbel

Maria Porrini

Roberto Scala

Kyong-Min Kim

Robert A Craven

Sadasivam Chandrasekhar

Larry E Drafall

Fabrizio Leoni

Paolo Collareta

Vladimir V Vornokov

Maria Giovanna Pretto

Vladimir Voronkov

Alessandro Corradi

Marco Bricchetti

Graham R Booker

Zsolt J Laczik

Galina I Voronkova

Anna V Batunina

Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.

Apparatus for stressing semiconductor substrates

A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1&#xd7;10atoms/cmand/or germanium at a concentration of at least about 1&#xd7;10atoms/cm, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.

High resistivity single crystal silicon ingot and wafer having improved mechanical strength

A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1&#xd7;1014 atoms/cm3 and/or germanium at a concentration of at least about 1&#xd7;1019 atoms/cm3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.

The disclosure is directed to a method to recover the gate oxide integrity yield of a silicon wafer after rapid thermal anneal in an ambient atmosphere comprising a nitrogen containing gas, such as NHor N. Generally, rapid thermal anneals in an ambient atmosphere comprising a nitrogen containing gas, such as NHor Nto thereby imprint an oxygen precipitate profile can degrade the GOI yield of a silicon wafer by exposing as-grown crystal defects (oxygen precipitate) and vacancies generated by the silicon nitride film. The present invention restores GOI yield by stripping the silicon nitride layer, which is followed by wafer oxidation, which is followed by stripping the silicon oxide layer.

Method of treating silicon wafers to have intrinsic gettering and gate oxide integrity yield

A method for controlling oxygen precipitation in a single crystal silicon wafer having a wafer resistivity of less than about 10 milliohm-cm is provided so that the wafer has uniformly high oxygen precipitation behavior from the central axis to the circumferential edge. The single crystal silicon wafer comprises an additional dopant selected from among carbon, arsenic, and antimony.

Oxygen precipitation in heavily doped silicon wafers sliced from ingots grown by the Czochralski method

Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.

Processes and apparatus for preparing heterostructures with reduced strain by radial compression

Processes and apparatus for preparing heterostructures with reduced strain by radial distension

Processes for suppressing minority carrier lifetime degradation in silicon wafers are disclosed. The processes involve quench cooling the wafers to increase the density of nano-precipitates in the silicon wafers and the rate at which interstitial atoms are consumed by the nano-precipitates.

Silicon wafers with suppressed minority carrier lifetime degradation

Processes for the treatment of silicon wafers to form a high density non-uniform distribution of oxygen precipitate nuclei therein such that, upon being subjected to the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, the wafers form oxygen precipitates in the bulk and a precipitate-free zone near the surface are disclosed. The processes involve activation of inactive oxygen precipitate nuclei by performing heat treatments between about 400&#xb0; C. and about 600&#xb0; C. for at least about 1 hour.

Production of high precipitate density wafers by activation of inactive oxygen precipitate nuclei

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London, United Kingdom

Robert J Falster