For the Inventor, By the Inventor

Enter assignee name

Singapore, Singapore

Advanpack Solutions Pte Ltd.

Calculating rank

USPTO Granted Patents = 44

% Expired Patents = 2.3

Forward Citations = 1,342

Loading Chart...

Loading Chart...

45 inventors (with patents filed for the assignee):

Hwee-Seng Jimmy Chew (18 out of 18 patents)

Shoa-Siong Lim (14 out of 14 patents)

Kian-Hock Lim (8 out of 8 patents)

4. Chee Kian Ong (6 out of 7 patents)

5. Shoa Siong Lim (5 out of 6 patents)

6. Tan Kim Hwee (5 out of 5 patents)

7. Oviso Dominador Jr Fortaleza (4 out of 4 patents)

8. Kee Kwang Lau (4 out of 4 patents)

9. Roman Perez (4 out of 4 patents)

10. Alex Chew (3 out of 3 patents)

11. Tie Wang (3 out of 4 patents)

12. Antonio Dimaano (3 out of 3 patents)

13. Jimmy Hwee-Seng Chew (2 out of 2 patents)

14. Bin Chichik Abd Razak (2 out of 2 patents)

15. Ong Chee Kian (2 out of 2 patents)

Core Competencies:

Semiconductor Structure

Multi-layer Substrate

Flip Chip Package

Etch-back Type Package

Fine Pitch Packaging

Chip Grid Array

Manufacturing Method

Pillar Connections

Substrate Structure

Device Carrier

Interconnections

Encapsulation

44 patents: Sort by Forward Citations

1. 10763133 - Semiconductor structure and semiconductor package device using the same (2020-09-01),

2. 10446457 - Multi-layer substrate for semiconductor packaging (2019-10-15),

3. 10154588 - Manufacturing method of semiconductor package (2018-12-11),

4. 10109503 - Method of manufacturing semiconductor package device (2018-10-23),

5. 10049950 - Multi-layer substrate for semiconductor packaging (2018-08-14),

6. 9892916 - Manufacturing method of package substrate and package manufacturing method of semiconductor device (2018-02-13),

7. 9847268 - Semiconductor package and manufacturing method thereof (2017-12-19),

8. 9754899 - Semiconductor structure and method of fabricating the same (2017-09-05),

9. 9723717 - Substrate structure, semiconductor package device, and manufacturing method of semiconductor package (2017-08-01),

10. 9653323 - Manufacturing method of substrate structure having embedded interconnection layers (2017-05-16),

11. 9583449 - Semiconductor package (2017-02-28),

12. 9396982 - Semiconductor device carrier for fine pitch packaging miniaturization and manufacturing method thereof (2016-07-19),

13. 9379044 - Package carrier, package carrier manufacturing method, package structure for semiconductor device and manufacturing method thereof (2016-06-28),

14. 9362206 - Chip and manufacturing method thereof (2016-06-07),

15. 9305868 - Manufacturing method of forming an etch-back type semiconductor package with locking anchorages (2016-04-05),

Company Overview

Advanpack Solutions Pte Ltd, based in Singapore, specializes in advanced semiconductor packaging technologies. The company focuses on innovative solutions such as multi-layer substrates, fine pitch packaging, and wafer-level chip scale packages. With expertise in pillar bump technology and embedded interconnection layers, Advanpack is committed to enhancing the performance and reliability of semiconductor devices. Their research and development efforts are aimed at addressing the evolving needs of the electronics industry, positioning them as a key player in the semiconductor packaging sector.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 27 2026

44 Patents

#66 in Singapore

#66 in Singapore

#15,771 in the World

Singapore, Singapore

Advanpack Solutions Pte Ltd.

Forward Citations = 1,342

45 inventors:

Hwee-Seng Jimmy Chew (18 out of 18 patents)

Shoa-Siong Lim (14 out of 14 patents)

Kian-Hock Lim (8 out of 8 patents)

4. Chee Kian Ong (6 out of 7 patents)

5. Shoa Siong Lim (5 out of 6 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Advanpack Solutions Pte Ltd.. Retrieved from https://idiyas.com/company/advanpack-solutions

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

Loading…