The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2016

Filed:

Nov. 26, 2008
Applicants:

Hwee-seng Jimmy Chew, Singapore, SG;

Chee Kian Ong, Singapore, SG;

Bin Chichik Abd. Razak, Singapore, SG;

Inventors:

Hwee-Seng Jimmy Chew, Singapore, SG;

Chee Kian Ong, Singapore, SG;

Bin Chichik Abd. Razak, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/683 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/6835 (2013.01); H01L 23/49816 (2013.01); H01L 23/49861 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2221/68345 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16 (2013.01); H01L 2924/00013 (2013.01); H01L 2924/01068 (2013.01); H01L 2924/01079 (2013.01);
Abstract

A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.


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