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For the Inventor, By the Inventor

St. Nazaire les Eymes, France

Takeshi Akatsu

This inventor holds 21 USPTO granted patents and 1 published patent application and 3 EPO patents, primarily in Semiconductor Fabrication. Top assignees: S.o.i.tec Silicon on Insulator Technologies, S.o.i. Tec Silicon on Insulator Technologies, S.a., Commissariat a L'energie Atomique Et Aux Energies Alternatives. Active years: 2006-2011.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Takeshi Akatsu. Retrieved from https://idiyas.com/inventor/takeshi-akatsu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 21 

% Patents Active = 90.5


Average Co-Inventor Count = 3.0

ph-index = 7

Forward Citations = 104(Granted Patents)


Location History:

  • Saint Nazaire les Eymes, FR (2006 - 2009)
  • St Nazaire les Eymes, FR (2006 - 2010)
  • St. Nazaire les Eymes, FR (2007 - 2011)

Company Filing History:

goldMedal16 out of 214 
 
S.o.i.tec Silicon on Insulator Technologies
 patents
silverMedal5 out of 86 
 
S.o.i. Tec Silicon on Insulator Technologies, S.a.
 patents
bronzeMedal1 out of 8,827 
 
Commissariat a L'energie Atomique Et Aux Energies Alternatives
 patents
where one patent can have more than one assignee

Years Active: 2006-2011

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Areas of Expertise:
Release Substrate
Semiconductor Wafer
Thin Layer Transfer
Multi-Gate FET
Atomic Implantation
Thermal Treatment
Multilayer Structure
Recycling Techniques
Epitaxial Growth
Buffer Layer
Surface Roughness
Sequential Implantations
21 patents (USPTO):Explore Patents
1. 8012289 - Method of fabricating a release substrate (2011-09-06),
2. 7776716 - Method for fabricating a semiconductor on insulator wafer (2010-08-17),
3. 7602046 - Recycling by mechanical means of a wafer comprising a multilayer structure after taking-off a thin layer thereof (2009-10-13),
4. 7544265 - Method of fabricating a release substrate (2009-06-09),
5. 7476930 - Multi-gate FET with multi-layer channel (2009-01-13),
6. 7449394 - Atomic implantation and thermal treatment of a semiconductor layer (2008-11-11),
7. 7378729 - Recycling a wafer comprising a buffer layer, after having separated a thin layer therefrom (2008-05-27),
8. 7375008 - Recycling by mechanical means of a wafer comprising a multilayer structure after taking-off a thin layer thereof (2008-05-20),
9. 7326628 - Thin layer transfer method utilizing co-implantation to reduce blister formation and to surface roughness (2008-02-05),
10. 7323398 - Method of layer transfer comprising sequential implantations of atomic species (2008-01-29),
11. 7285495 - Methods for thermally treating a semiconductor layer (2007-10-23),
12. 7282449 - Thermal treatment of a semiconductor layer (2007-10-16),
13. 7276428 - Methods for forming a semiconductor structure (2007-10-02),
14. 7265435 - Method for implanting atomic species through an uneven surface of a semiconductor layer (2007-09-04),
15. 7256075 - Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer (2007-08-14),

Title: The Innovative Path of Takeshi Akatsu

Introduction

Takeshi Akatsu, located in Saint Nazaire les Eymes, France, is an accomplished inventor whose contributions to the field of semiconductor technology are notable. With a remarkable portfolio that includes 21 patents, Akatsu has made significant advancements in methods related to semiconductor fabrication.

Latest Patents

Among his latest patents, Akatsu introduced a novel "Method of Fabricating a Release Substrate." This invention details a method for creating a release substrate produced from semiconductor materials, emphasizing a reversible connection between two substrate release layers. Notably, the method maintains the bonding energy of this connection even during heat treatment, which is essential for enhancing the reliability of semiconductor applications.

Another significant patent is the "Method for Fabricating a Semiconductor on Insulator Wafer." This method involves the fabrication of semiconductor on insulator wafers by utilizing a source substrate with an epitaxial semiconductor layer. The process includes attaching this substrate to a handle substrate, detaching it at a predetermined area, and subsequently removing a layer to create the desired wafer. An oxygen diffusion barrier layer can also be provided, showcasing the innovative nature of his work in this domain.

Career Highlights

Throughout his career, Takeshi Akatsu has worked with prominent companies in the semiconductor industry, including S.O.I. Tec Silicon on Insulator Technologies. His expertise and innovative approaches have led him to become a respected figure in the field, recognized for his contributions to semiconductor research and development.

Collaborations

Akatsu has collaborated with talented professionals, including Bruno Ghyselen and Cécile Aulnette. Their combined efforts have fostered advancements in semiconductor technology, driving innovation within their respective projects and initiatives.

Conclusion

In conclusion, Takeshi Akatsu stands out as a remarkable inventor whose contributions to the semiconductor industry have paved the way for new technologies and methodologies. His dedication to innovation and collaboration continues to inspire others in the field. As he progresses in his career, the impact of his inventions will undoubtedly resonate within the technological landscape for years to come.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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