S.o.i.tec Silicon on Insulator Technologies

S.o.i. Tec Silicon on Insulator Technologies, S.a.

Commissariat À L'energie Atomique (Cea)

Soitec

Takeshi Akatsu

Bruno Ghyselen

Cécile Aulnette

Bénédite Osternaud

Nguyet-Phuong Nguyen

Nicolas Daval

Olivier Rayssac

Bruce Faure

Pierre Rayssac, Legal Representative

Yves-Mathieu Vaillant

Hubert Moriceau

Nadia Ben Mohamed

Chrystel Deguet

Konstantin Bourdelle

Thomas Signamarcheix

Alice Boussagol

Loic Sanchez

Gisèle Rayssac, Legal Representative

Yves Mathieu Le Vaillant

Yves-Mathieu Le Vaillant

Fréderic Allibert

Gabriela Suciu

Bénédicte Osternaud

Richard Fontaniere

The invention relates to a method of fabricating a release substrate produced from semiconductor materials, the method comprising creating a reversible connection between two substrate release layers characterized in that the reversible connection is formed by a connecting layer produced using a first material as the basis, the connecting layer further comprising a nanoparticle concentrating zone of a second material disposed to facilitate release of the substrate, the first and second materials being selected to maintain the bonding energy of the reversible connection substantially constant even when the substrate is exposed to heat treatment.

Method of fabricating a release substrate

A method for fabricating semiconductor on insulator wafers by providing a semiconductor substrate or a substrate that includes an epitaxial semiconductor layer as a source substrate, attaching the source substrate to a handle substrate to form a source handle assembly and detaching the source substrate at a predetermined splitting area provided inside the source substrate and being essentially parallel to its main surface, to remove a layer from the source handle assembly to thereby create the semiconductor on insulator wafer. A diffusion barrier layer, in particular, an oxygen diffusion barrier layer can be provided on the source substrate. In addition the invention relates to the corresponding semiconductor on insulator wafers that are produced by the method.

Method for fabricating a semiconductor on insulator wafer

The invention relates to a recyclable donor wafer that includes a substrate and a formed layer thereon, wherein the formed layer has a thickness sufficient to provide (a) at least two useful layers for detachment therefrom and (b) additional material that can be removed to planarize exposed surfaces of the useful layers prior to detachment from the donor wafer.

Recycling by mechanical means of a wafer comprising a multilayer structure after taking-off a thin layer thereof

The invention concerns a field-effect transistor with a drain, a source, a channel in electrical contact with the source and the drain, and at least one gate, so as to apply an electric field to the channel when each gate is polarized, where the channel has a multi-layer structure with at least three layers, and with at least one of the layers of the multi-layer structure having electrical properties that are substantially different from those of another layer of the multi-layer structure, and wherein a single gate or two gates are arranged substantially perpendicular to a reference plane of the channel defined by an interface plane between two layers of the multi-layer structure.

Multi-gate FET with multi-layer channel

Methods for forming a semiconductor structure are described. In an embodiment, the technique includes providing a donor wafer having a first semiconductor layer and a second semiconductor layer on the first layer and having a free surface; coimplanting two different atomic species through the free surface of the second layer to form a zone of weakness zone in the first layer; bonding the free surface of the second layer to a host wafer; and supplying energy to detach at the zone of weakness a semiconductor structure comprising the host wafer, the second layer and a portion of the first layer. Advantageously, the donor wafer includes a SiGe layer, and the co-implantation of atomic species is conducted according to implantation parameters adapted to enable a first species to form the zone of weakness in the SiGe layer, and to enable a second species to provide a concentration peak located beneath the zone of weakness in the donor wafer to thus minimize surface roughness resulting from detachment at the zone of weakness.

Atomic implantation and thermal treatment of a semiconductor layer

A donor wafer resulting from a method of recycling the wafer after detaching at least one useful layer. The donor wafer includes a substrate; a buffer structure on the substrate; a protective layer associated with the buffer structure; and a post detachment layer located above the buffer structure and presenting projections or rough portions on its surface. The protective layer prevents removal of the entire buffer structure when the post detachment layer is removed.

Recycling a wafer comprising a buffer layer, after having separated a thin layer therefrom

The invention relates to a method of re-forming a useful layer on a donor wafer after taking off a useful layer formed of a material chosen from among semiconductor materials. The donor wafer includes in succession a substrate and a taking-off structure, the taking-off structure includes the taken-off useful layer before taking-off. The method includes a removal of material involving a portion of the donor wafer on the side where the useful layer has been taken off. The material is removed by mechanical means so as to preserve a portion of the taking-off structure to form at least one other useful layer which can be taken off after re-forming, without adding additional material to the wafer.

A method for producing a semiconductor structure by conducting controlled co-implanting of at least first and second different atomic species into a donor substrate to create an embrittlement zone which defines a thin layer of donor material to be transferred. Implantation energies are selected so that the first and second species are respectively distributed in the donor wafer according to a repartition profile that presents a spreading zone in which each species is mainly distributed at a maximum concentration peak. The implantation doses and energies of the first and second species are selected such that the second species is implanted deeper in the embrittlement zone than the first species spreading zone. The donor substrate is detached at the embrittlement zone to transfer the thin layer to the support substrate while minimizing blister formation in and surface roughness of the transferred layer. Preferably, the implantation dose of the first species is between about 40 to 60 percent of all implantation doses. This method is preferably utilized for forming or producing SeOI (Semiconductor On Insulator) structures.

Thin layer transfer method utilizing co-implantation to reduce blister formation and to surface roughness

A method of manufacturing a crystalline wafer that includes implanting first atomic species in a donor substrate to form a region of weakness at a first depth therein and configured to facilitate detachment of a first layer of the donor substrate from a remaining portion of the donor substrate. The first layer and remaining portion are disposed on opposite sides of the region of weakness. The method also includes implanting second atomic species in the donor substrate to form a gettering region at a second depth therein that is different than the first depth to reduce or minimize migration of the implanted first atomic species past the gettering region. This reduces or minimizes an increase in roughness of a surface produced on the first layer after detachment thereof from the remaining portion at the region of weakness.

Method of layer transfer comprising sequential implantations of atomic species

A method for thermally treating a semiconductor layer is described. An embodiment of the technique includes implanting atomic species into a first surface of a donor wafer to form a zone of weakness at a predetermined depth that defines the thickness of a transfer layer, bonding the first surface of the donor wafer to a host wafer, supplying energy to detach the transfer layer from the donor wafer at the zone of weakness, and conducting a recovery operation on the transfer layer. The recovery operation is conducted after detachment but while the layer remains in contact with the donor wafer. The recovery operation includes heat treating the transfer layer for a predetermined duration at a recovery temperature that is lower than a re-adhesion temperature at which the transfer layer would re-adhere to the donor wafer, to improve the crystalline quality and the surface roughness of the transfer layer.

Methods for thermally treating a semiconductor layer

A method for thermally treating a silicon germanium semiconductor layer from a donor wafer is described. An embodiment of the technique includes co-implanting atomic species into a first surface of the donor wafer to form a zone of weakness at a predetermined depth that defines the thickness of a transfer layer, bonding the first surface of the donor wafer to a host wafer, supplying energy to detach the transfer layer from the donor wafer at the zone of weakness, and conducting a recovery operation on the transfer layer. The recovery operation is conducted after detachment but while the layer remains in contact with the donor wafer. The recovery operation includes heat treating the transfer layer for a predetermined duration at a recovery temperature that is lower than a re-adhesion temperature at which the transfer layer would re-adhere to the donor wafer, to improve the crystalline quality and the surface roughness of the transfer layer. The co-implanting step preferably includes implanting hydrogen and helium.

Thermal treatment of a semiconductor layer

Methods for forming a semiconductor structure are described. In an embodiment, the technique includes providing a donor wafer having a first semiconductor layer and a second semiconductor layer on the first layer and having a free surface, implanting atomic species through the free surface of the second layer to form a zone of weakness zone in the first layer, and bonding the free surface of the second layer to a host wafer. The method also includes supplying energy to detach at the zone of weakness a semiconductor structure comprising the host wafer, the second layer and a portion of the first layer, conducting a bond strengthening step on the structure after detachment at a temperature of less than about 800&#xb0; C. to improve the strength of the bond between the second layer and the host wafer, and selectively etching the first layer portion to remove it from the structure and to expose a surface of the second layer. The implanting step includes implantation parameters chosen to minimize surface roughness resulting from detachment at the zone of weakness.

Methods for forming a semiconductor structure

A method for implanting atomic species through an uneven surface of a semiconductor layer. The technique includes applying a covering layer upon the uneven surface in an amount sufficient and in a manner to increase surface uniformity. The method also includes implanting atomic species through the covering layer and uneven surface to obtain a more uniform depth of implantation of the atomic species in the layer.

Method for implanting atomic species through an uneven surface of a semiconductor layer

The invention relates to a method of transferring useful layers from a donor wafer which includes a multi-layer structure on the surface of the donor wafer that has a thickness sufficient to form multiple useful layers for subsequent detachment. The layers may be formed of materials having sufficiently different properties such that they may be selectively removed. The layers of material may also include sub-layers that can be selectively removed from each other.

Growing community of inventors

Saint Nazaire les Eymes, France

Takeshi Akatsu