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For the Inventor, By the Inventor

Crolles, France

S.o.i. Tec Silicon on Insulator Technologies, S.a.


USPTO Granted Patents = 86


Forward Citations = 1,053

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92 inventors (with patents filed for the assignee):

goldMedal Bruno Ghyselen (30 out of 111 patents)

silverMedal Fabrice Letertre (21 out of 83 patents)

bronzeMedal Olivier Rayssac (15 out of 48 patents)

4.  Christophe Maleville (14 out of 56 patents)

5.  Cécile Aulnette (11 out of 25 patents)

6.  Eric Neyret (9 out of 24 patents)

7.  Walter Schwarzenbach (6 out of 52 patents)

8.  Thibaut Maurice (6 out of 7 patents)

9.  Carlos Mazure (5 out of 48 patents)

10.  Takeshi Akatsu (5 out of 21 patents)

11.  Bénédite Osternaud (5 out of 9 patents)

12.  Hubert Moriceau (4 out of 83 patents)

13.  Thierry Barge (4 out of 26 patents)

14.  Nyles Wynn Cody (3 out of 48 patents)

15.  Bruce Faure (3 out of 33 patents)


Core Competencies:
Epitaxial Methods
Strained Layers
Semiconductor Buffer Structures
Thermal Processing Equipment
Wafer Fabrication
Multilayer Semiconductor
Layer Transfer Method
Bonding Surface Preparation
Heat Treatment
Substrate Recycling
Atomic Species Implantation
High Quality Useful Layer

86 patents:

1. 8178427 - Epitaxial methods for reducing surface dislocation density in semiconductor materials (2012-05-15),
2. 7825401 - Strained layers within semiconductor buffer structures (2010-11-02),
3. 7785995 - Semiconductor buffer structures (2010-08-31),
4. 7608526 - Strained layers within semiconductor buffer structures (2009-10-27),
5. 7232743 - Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same (2007-06-19),
6. 7232738 - Device and method for cutting an assembly (2007-06-19),
7. 7229898 - Methods for fabricating a germanium on insulator wafer (2007-06-12),
8. 7225095 - Thermal processing equipment calibration method (2007-05-29),
9. 7221038 - Method of fabricating substrates and substrates obtained by this method (2007-05-22),
10. 7217639 - Method of manufacturing a material compound wafer (2007-05-15),
11. 7190029 - Preventive treatment method for a multilayer semiconductor wafer (2007-03-13),
12. 7189632 - Multifunctional metallic bonding (2007-03-13),
13. 7189304 - Substrate layer cutting device and method (2007-03-13),
14. 7187162 - Tools and methods for disuniting semiconductor wafers (2007-03-06),
15. 7182234 - Substrate cutting device and method (2007-02-27),
S.o.i. Tec Silicon on Insulator Technologies, S.a. is a leading semiconductor materials company that specializes in the design and production of silicon-on-insulator substrates, enabling the manufacturing of advanced semiconductor devices with enhanced performance and energy efficiency. With a strong focus on innovation and technology leadership, S.o.i. Tec Silicon on Insulator Technologies, S.a. is a trusted partner for the semiconductor industry.
This text is generated by artificial intelligence and may not be accurate.

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USPTO Data Jan 1 1976 - Dec 2 2025

86 Patents

#3 in Crolles

#293 in France

#8,570 in the World

...
Crolles, France

S.o.i. Tec Silicon on Insulator Technologies, S.a.

Forward Citations = 1,053

92 inventors:

goldMedal Bruno Ghyselen (30 out of 111 patents)

silverMedal Fabrice Letertre (21 out of 83 patents)

bronzeMedal Olivier Rayssac (15 out of 48 patents)

4.  Christophe Maleville (14 out of 56 patents)

5.  Cécile Aulnette (11 out of 25 patents)

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