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For the Inventor, By the Inventor

Sassenage, France

Eric Neyret

This inventor holds 24 USPTO granted patents and 2 published patent applications and 10 EPO patents, primarily in Semiconductor Fabrication. Top assignees: S.o.i.tec Silicon on Insulator Technologies, S.o.i. Tec Silicon on Insulator Technologies, S.a., Soitec. Active years: 2005-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Eric Neyret. Retrieved from https://idiyas.com/inventor/eric-neyret

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 24 

% Patents Active = 91.7

 

Average Co-Inventor Count = 2.2

ph-index = 7

Forward Citations = 119(Granted Patents)


Location History:

  • Sassenege, FR (2011)
  • Gaujac, FR (2013)
  • Sassenage, FR (2005 - 2014)

Company Filing History:

goldMedal12 out of 214 
 
S.o.i.tec Silicon on Insulator Technologies
 patents
silverMedal9 out of 86 
 
S.o.i. Tec Silicon on Insulator Technologies, S.a.
 patents
bronzeMedal3 out of 540 
 
Soitec
 patents

Years Active: 2005-2014

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Areas of Expertise:
Silicon-On-Insulator
Surface Roughness
Bonding Interface
Multilayer Wafer
Thin Layer Transfer
Defect Density
Heat Treatment
Process Configuration
Compound-Material Wafers
Preventive Treatment
Semiconductor Structure
24 patents (USPTO):Explore Patents
1. 8679944 - Progressive trimming method (2014-03-25),
2. 8461018 - Treatment for bonding interface stabilization (2013-06-11),
3. 8389412 - Finishing method for a silicon on insulator substrate (2013-03-05),
4. 8273636 - Process for the transfer of a thin layer formed in a substrate with vacancy clusters (2012-09-25),
5. 8216916 - Treatment for bonding interface stabilization (2012-07-10),
6. 7947571 - Method for fabricating a semiconductor on insulator substrate with reduced Secco defect density (2011-05-24),
7. 7939427 - Process for fabricating a substrate of the silicon-on-insulator type with reduced roughness and uniform thickness (2011-05-10),
8. 7883628 - Method of reducing the surface roughness of a semiconductor wafer (2011-02-08),
9. 7863158 - Treatment for bonding interface stabilization (2011-01-04),
10. 7749910 - Method of reducing the surface roughness of a semiconductor wafer (2010-07-06),
11. 7666758 - Process for fabricating a substrate of the silicon-on-insulator type with thin surface layer (2010-02-23),
12. 7514341 - Finishing process for the manufacture of a semiconductor structure (2009-04-07),
13. 7485545 - Method of configuring a process to obtain a thin layer with a low density of holes (2009-02-03),
14. 7405136 - Methods for manufacturing compound-material wafers and for recycling used donor substrates (2008-07-29),
15. 7285471 - Process for transfer of a thin layer formed in a substrate with vacancy clusters (2007-10-23),

Title: Inventor Eric Neyret - Revolutionizing Technology in Sassenage, FR

Introduction: Eric Neyret is a visionary inventor based in Sassenage, France, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Eric Neyret holds several patents in the areas of renewable energy, artificial intelligence, and sustainable technologies, showcasing his commitment to creating a more sustainable future.

Career Highlights: With a career spanning over two decades, Eric Neyret has worked with leading research institutions and technology companies to develop cutting-edge solutions that have revolutionized various industries.

Collaborations: Throughout his career, Eric Neyret has collaborated with top engineers, scientists, and researchers from around the world, fostering a culture of innovation and excellence in all his projects.

Conclusion: Eric Neyret's passion for innovation and his relentless pursuit of technological advancement continue to inspire the next generation of inventors and entrepreneurs worldwide.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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