Taek-Soo Jeon

This inventor holds 15 USPTO granted patents and 1 published patent application. Top assignee: Samsung Electronics Co., Ltd.. Active years: 2005-2019.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Taek-Soo Jeon. Retrieved from https://idiyas.com/inventor/taek-soo-jeon

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 15 (Patent Applications = 1)

% Patents Active = 80.0

Average Co-Inventor Count = 5.0

ph-index = 4

Forward Citations = 42(Granted Patents)

Location History:

Gyeonggi, KR (2008)
Gyeonggi-do, KR (2005 - 2016)
Yongin-si, KR (2008 - 2019)

Company Filing History:

15 out of 132,108

Samsung Electronics Co., Ltd.

patents

Years Active: 2005-2019

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15 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 10177042 - Semiconductor device and method for fabricating the same (2019-01-08),

2. 9929252 - Method of forming thin film and method of manufacturing semiconductor device (2018-03-27),

3. 9786761 - Integrated circuit device having an interfacial layer and method of manufacturing the same (2017-10-10),

4. 9412842 - Method for fabricating semiconductor device (2016-08-09),

5. 9054189 - Semiconductor device and method for fabricating the same (2015-06-09),

6. 8928152 - Semiconductor device including contact plug and method of manufacturing the same (2015-01-06),

7. 8697570 - Semiconductor device including contact plug and method of manufacturing the same (2014-04-15),

8. 8039344 - Methods of forming a capacitor structure and methods of manufacturing a semiconductor device using the same (2011-10-18),

9. 7892958 - Methods of fabricating semiconductor devices having transistors with different gate structures (2011-02-22),

10. 7727841 - Method of manufacturing semiconductor device with dual gates (2010-06-01),

11. 7531881 - Semiconductor devices having transistors with different gate structures and methods of fabricating the same (2009-05-12),

12. 7494859 - Semiconductor device having metal gate patterns and related method of manufacture (2009-02-24),

13. 7399670 - Methods of forming different gate structures in NMOS and PMOS regions and gate structures so formed (2008-07-15),

14. 7390719 - Method of manufacturing a semiconductor device having a dual gate structure (2008-06-24),

15. 6930062 - Methods of forming an oxide layer in a transistor having a recessed gate (2005-08-16),

Title: The Innovations of Taek-Soo Jeon

Introduction

Taek-Soo Jeon is a prominent inventor based in Yongin-si, South Korea. He has made significant contributions to the field of semiconductor technology, holding a total of 15 patents. His work has been instrumental in advancing the capabilities of semiconductor devices.

Latest Patents

Among his latest patents is a semiconductor device and method for fabricating the same. This invention includes a first trench and a second trench, a liner pattern along a portion of side surfaces and along bottom surfaces of the trenches, a work function metal, and barrier metals with varying thicknesses. Another notable patent is a method of forming a thin film and manufacturing a semiconductor device. This method involves creating an interface layer stack on a semiconductor substrate through a series of surface treatments under different atmospheres.

Career Highlights

Taek-Soo Jeon is currently employed at Samsung Electronics Co., Ltd., where he continues to innovate in semiconductor technology. His expertise has led to advancements that enhance the performance and efficiency of semiconductor devices.

Collaborations

He has collaborated with notable colleagues such as Yu-Gyun Shin and Sang-Bom Kang, contributing to a dynamic research environment that fosters innovation.

Conclusion

Taek-Soo Jeon's contributions to semiconductor technology through his patents and collaborations highlight his role as a leading inventor in the field. His work continues to influence the future of semiconductor devices and their applications.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

1 patent pending: