Samsung Electronics Co., Ltd.

Taek-Soo Jeon

Yu-Gyun Shin

Sang-Bom Kang

Hye-Lan Lee

Hag-Ju Cho

Sang-Jin Hyun

Bong-hyun Kim

Seong-Geon Park

Jae-hong Seo

Dae-Hyun Kim

Jin-bum Kim

Hoon-Joo Na

Hag-ju Cho

Won-Seok Yoo

Hu-Yong Lee

Won-Keun Chung

Ho-kyun An

Judson Robert Holt

Henry K Utomo

Bon-Young Koo

Dong-Soo Lee

Han-jin Lim

Hong-bae Park

Seok-Woo Nam

Beom-jun Jin

Sang-Yong Kim

Sug-hun Hong

Sang-jin Hyun

Tae-Ho Cha

Jeong-Do Ryu

Kyung-Bum Koo

Sun-gyu Choi

Young-suk Chai

A semiconductor device includes a first trench and a second trench, a liner pattern along a portion of side surfaces and along bottom surfaces of the first and the second trenches, respectively, a work function metal in the first and the second trenches and on the liner pattern, respectively, a first barrier metal in the first trench and on the work function metal, and having a first thickness, a second barrier metal in the second trench and on the work function metal, and having a second thickness thicker than the first thickness, and a first fill metal on the first barrier metal.

Semiconductor device and method for fabricating the same

A method of forming a thin film includes forming an interface layer stack on a semiconductor substrate. Forming the interface layer stack may include performing a first surface treatment on the semiconductor substrate under a reducing atmosphere. Forming the interface layer stack may include performing a second surface treatment on the semiconductor substrate. The first surface treatment may be performed under a reducing atmosphere and the second surface treatment may be performed under a nitridation atmosphere. The first surface treatment may include forming a lower interface layer on a surface of the semiconductor substrate and the second surface treatment may include forming an upper interface layer. The first surface treatment may include selectively removing at least one oxide material from a native oxide film on the semiconductor substrate.

Method of forming thin film and method of manufacturing semiconductor device

An integrated circuit device includes a substrate including an active region, an interfacial layer including a lower insulating layer on the active region, the lower insulating layer doped with a chalcogen element having an atomic weight equal to or greater than 16, a gate insulation layer on the interfacial layer, and a gate electrode on the gate insulation layer.

Integrated circuit device having an interfacial layer and method of manufacturing the same

A gate pattern is formed on a first region of a substrate. An epitaxial layer is formed on a second region of the substrate. A recess is formed in the second region of the substrate by etching the epitaxial layer and the substrate underneath. The first region is adjacent to the second region.

Method for fabricating semiconductor device

A semiconductor device is provided. An active fin protrudes from a substrate. A gate structure is formed on the substrate and the active fin. The gate structure extends in a first direction. The gate structure crosses a first region of the active fin in a second direction. A first epitaxial layer is formed on a second region of the active fin. The second region of the active fin is not covered with the gate structure. A second epitaxial layer is formed on the first epitaxial layer, the second epitaxial layer including an impurity. The first epitaxial layer includes a blocking material. The blocking material of the first epitaxial layer prevents the impurity of the second epitaxial layer from passing through the first epitaxial layer to block diffusion of the impurity to a channel region formed in the first region of the active fin.

A semiconductor device includes a substrate having a conductive area, a first pattern formed on the substrate and having a contact hole through which the conductive area is exposed, and a contact plug in the contact hole. The contact plug includes first and second silicon layers. The first silicon layer, formed from a first compound including at least two silicon atoms, is formed in the contact hole to contact a top surface of the conductive area and a side wall of the first pattern. The second silicon layer, formed from a second compound including a number of silicon atoms less than the number of the silicon atoms of the first compound, is formed on the first silicon layer and fills a remaining space of the contact hole, the second silicon layer being spaced apart from the first pattern at an entrance of the contact hole.

Semiconductor device including contact plug and method of manufacturing the same

In a method of forming a capacitor, a seed stopper and a sacrificial layer is formed on an insulating interlayer having a plug therethrough. An opening is formed through the sacrificial layer and the seed stopper to expose the plug. A seed is formed on an innerwall of the opening. A lower electrode is formed covering the seed on the innerwall of the opening. The sacrificial layer and the seed are removed. A dielectric layer and an upper electrode are sequentially formed on the lower electrode.

Methods of forming a capacitor structure and methods of manufacturing a semiconductor device using the same

A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a polysilicon layer contacts a gate insulation film while the other transistor includes a gate structure in which a metal layer contacts a gate insulation film.

Methods of fabricating semiconductor devices having transistors with different gate structures

In a semiconductor device with dual gates and a method of manufacturing the same, a dielectric layer and first and second metallic conductive layers are successively formed on the semiconductor substrate having first and second regions. The second metallic conductive layer which is formed on the first metallic conductive layer of the second region is etched to form a metal pattern. The first metallic conductive layer is etched using the metal pattern as an etching mask. A polysilicon layer is formed on the dielectric layer and the metal pattern. The first gate electrode is formed by etching portions of the polysilicon layer, the metal pattern, and the first metallic conductive layer of the first region. The second gate electrode is formed by etching a portion of the polysilicon layer formed directly on the dielectric layer of the second region.

Method of manufacturing semiconductor device with dual gates

Semiconductor devices having transistors with different gate structures and methods of fabricating the same

A semiconductor device comprising a semiconductor substrate having a first impurity region and a second impurity region, a first gate pattern formed on the first impurity region, and a second gate pattern formed on the second impurity region is disclosed. The first gate pattern comprises a first gate insulation layer pattern, a metal layer pattern having a first thickness, and a first polysilicon layer pattern. The second gate pattern comprises a second gate insulation layer pattern, a metal silicide layer pattern having a second thickness smaller than the first thickness, and a second polysilicon layer pattern. The metal silicide layer pattern is formed from a material substantially the same as the material from which the metal layer pattern is formed. A method for manufacturing the semiconductor device is also disclosed.

Semiconductor device having metal gate patterns and related method of manufacture

A method of forming transistor gate structures in an integrated circuit device can include forming a high-k gate insulating layer on a substrate including a first region to include PMOS transistors and a second region to include NMOS transistors. A polysilicon gate layer can be formed on the high-k gate insulating layer in the first and second regions. A metal silicide gate layer can be formed directly on the high-k gate insulating layer in the first region and avoiding forming the metal-silicide in the second region. Related gate structures are also disclosed.

Methods of forming different gate structures in NMOS and PMOS regions and gate structures so formed

A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed to have a reduced etching rate. A second metallic conductive layer is formed on the first metallic conductive layer to a second thickness that is greater than the first thickness. A portion of the second metallic conductive layer formed in a second area of the substrate is removed using an etching selectivity. A first gate structure having a first metallic gate including the first and the second metallic conductive layers is formed in a first area of the substrate. A second gate structure having a second metallic gate is formed in the second area. A gate dielectric layer is not exposed to an etching chemical due to the first metallic conductive layer, so its dielectric characteristics are not degraded.

Method of manufacturing a semiconductor device having a dual gate structure

A method of forming an oxide layer on a semiconductor substrate includes thermally oxidizing a surface of the substrate to form an oxide layer on the substrate, and then exposing the oxide layer to an ambient including predominantly oxygen radicals to thereby thicken the oxide layer. Related methods of fabricating a recessed gate transistor are also discussed.

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Yongin-si, South Korea

Taek-Soo Jeon