The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 24, 2008
Filed:
Aug. 01, 2006
Taek-soo Jeon, Yongin-si, KR;
Yu-gyun Shin, Seongnam-si, KR;
Sang-bom Kang, Seoul, KR;
Hag-ju Cho, Seoul, KR;
Hye-lan Lee, Hwaseong-si, KR;
Sang-yong Kim, Yongin-si, KR;
Taek-Soo Jeon, Yongin-si, KR;
Yu-Gyun Shin, Seongnam-si, KR;
Sang-Bom Kang, Seoul, KR;
Hag-Ju Cho, Seoul, KR;
Hye-Lan Lee, Hwaseong-si, KR;
Sang-Yong Kim, Yongin-si, KR;
Abstract
A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed to have a reduced etching rate. A second metallic conductive layer is formed on the first metallic conductive layer to a second thickness that is greater than the first thickness. A portion of the second metallic conductive layer formed in a second area of the substrate is removed using an etching selectivity. A first gate structure having a first metallic gate including the first and the second metallic conductive layers is formed in a first area of the substrate. A second gate structure having a second metallic gate is formed in the second area. A gate dielectric layer is not exposed to an etching chemical due to the first metallic conductive layer, so its dielectric characteristics are not degraded.