Runsheng Wang

This inventor holds 14 USPTO granted patents and 6 published patent applications. Top assignees: Peking University, Cadence Design Systems, Inc.. Active years: 2012-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Runsheng Wang. Retrieved from https://idiyas.com/inventor/runsheng-wang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 14 (Patent Applications = 6)

% Patents Active = 57.1

Average Co-Inventor Count = 6.5

ph-index = 3

Forward Citations = 43(Granted Patents)

Company Filing History:

Cadence Design Systems, Inc.

patents

Years Active: 2012-2020

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14 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 10621386 - Method of bias temperature instability calculation and prediction for MOSFET and FinFET (2020-04-14),

2. 9478641 - Method for fabricating FinFET with separated double gates on bulk silicon (2016-10-25),

3. 9099500 - Programmable array of silicon nanowire field effect transistor and method for fabricating the same (2015-08-04),

4. 9034702 - Method for fabricating silicon nanowire field effect transistor based on wet etching (2015-05-19),

5. 9018968 - Method for testing density and location of gate dielectric layer trap of semiconductor device (2015-04-28),

6. 8901644 - Field effect transistor with a vertical channel and fabrication method thereof (2014-12-02),

7. 8866507 - Method for testing trap density of gate dielectric layer in semiconductor device having no substrate contact (2014-10-21),

8. 8722312 - Method for fabricating semiconductor nano circular ring (2014-05-13),

9. 8592276 - Fabrication method of vertical silicon nanowire field effect transistor (2013-11-26),

10. 8564031 - High voltage-resistant lateral double-diffused transistor based on nanowire device (2013-10-22),

11. 8563370 - Method for fabricating surrounding-gate silicon nanowire transistor with air sidewalls (2013-10-22),

12. 8513067 - Fabrication method for surrounding gate silicon nanowire transistor with air as spacers (2013-08-20),

13. 8372752 - Method for fabricating ultra-fine nanowire (2013-02-12),

14. 8288238 - Method for fabricating a tunneling field-effect transistor (2012-10-16),

Title: The Innovative Journey of Inventor Runsheng Wang

Introduction: Runsheng Wang is a distinguished inventor hailing from Beijing, China, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Wang's latest patents focus on advancements in artificial intelligence, renewable energy, and sustainable technologies, showcasing his commitment to creating a more efficient and eco-friendly future.

Career Highlights: With a career spanning over two decades, Wang has held key positions in leading tech companies, where he spearheaded research and development projects that have resulted in numerous successful patents.

Collaborations: Wang has collaborated with top researchers, engineers, and scientists from around the world, fostering a culture of innovation and knowledge-sharing that has led to significant breakthroughs in various industries.

Conclusion: Runsheng Wang's dedication to pushing the boundaries of technology and his relentless pursuit of innovation continue to inspire the next generation of inventors and entrepreneurs worldwide.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

6 patents pending: