The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 2013
Filed:
Nov. 18, 2011
RU Huang, Beijing, CN;
Jiewen Fan, Beijing, CN;
Yujie Ai, Beijing, CN;
Shuai Sun, Beijing, CN;
Runsheng Wang, Beijing, CN;
Jibin Zou, Beijing, CN;
Xin Huang, Beijing, CN;
Ru Huang, Beijing, CN;
Jiewen Fan, Beijing, CN;
Yujie Ai, Beijing, CN;
Shuai Sun, Beijing, CN;
Runsheng Wang, Beijing, CN;
Jibin Zou, Beijing, CN;
Xin Huang, Beijing, CN;
Peking University, Beijing, CN;
Abstract
The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.