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For the Inventor, By the Inventor

Menands, NY, United States of America

Puneet Harischandra Suvarna

This inventor holds 20 USPTO granted patents and 1 published patent application, primarily in Vertical Transistor Technology. Top assignees: Globalfoundries Inc., Globalfoundries U.S. Inc., International Business Machines Corporation. Active years: 2018-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Puneet Harischandra Suvarna. Retrieved from https://idiyas.com/inventor/puneet-harischandra-suvarna

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 20 

% Patents Active = 95.0

Average Co-Inventor Count = 3.5

ph-index = 9

Forward Citations = 294(Granted Patents)


Location History:

  • Menands, NY (US) (2018 - 2020)
  • Albany, NY (US) (2018 - 2021)

Company Filing History:

goldMedal18 out of 5,671 
 
Globalfoundries Inc.
 patents
silverMedal1 out of 1,092 
 
Globalfoundries U.S. Inc.
 patents
bronzeMedal1 out of 166,409 
 
International Business Machines Corporation
 patents

Years Active: 2018-2021

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Areas of Expertise:
Thermoelectric Effect
Fin-based Devices
Complementary FET
Vertical FET
Self-aligned Contacts
Gate Control
Negative Capacitance
Integrated Circuits
Epitaxial Structures
Source/Drain Regions
Nano-sheet Devices
Trench Silicide
20 patents (USPTO):Explore Patents
1. 11038092 - Fin-based devices based on the thermoelectric effect (2021-06-15),
2. 10943992 - Transistor having straight bottom spacers (2021-03-09),
3. 10784171 - Vertically stacked complementary-FET device with independent gate control (2020-09-22),
4. 10510622 - Vertically stacked complementary-FET device with independent gate control (2019-12-17),
5. 10497798 - Vertical field effect transistor with self-aligned contacts (2019-12-03),
6. 10446659 - Negative capacitance integration through a gate contact (2019-10-15),
7. 10418449 - Circuits based on complementary field-effect transistors (2019-09-17),
8. 10347745 - Methods of forming bottom and top source/drain regions on a vertical transistor device (2019-07-09),
9. 10332969 - Negative capacitance matching in gate electrode structures (2019-06-25),
10. 10312154 - Method of forming vertical FinFET device having self-aligned contacts (2019-06-04),
11. 10304833 - Method of forming complementary nano-sheet/wire transistor devices with same depth contacts (2019-05-28),
12. 10256158 - Insulated epitaxial structures in nanosheet complementary field effect transistors (2019-04-09),
13. 10236379 - Vertical FET with self-aligned source/drain regions and gate length based on channel epitaxial growth process (2019-03-19),
14. 10236292 - Complementary FETs with wrap around contacts and methods of forming same (2019-03-19),
15. 10192867 - Complementary FETs with wrap around contacts and method of forming same (2019-01-29),

Title: Puneet Harischandra Suvarna: Pioneering Inventor from Menands, NY

Introduction: Puneet Harischandra Suvarna is a distinguished inventor hailing from Menands, NY, known for his groundbreaking contributions to the field of innovations and patents.

Latest Patents: Puneet Harischandra Suvarna holds several patents in various technological domains, showcasing his versatility and ingenuity in creating novel solutions to complex problems.

Career Highlights: With a career spanning over two decades, Puneet Harischandra Suvarna has consistently pushed the boundaries of technological advancements, leaving a lasting impact on the industry.

Collaborations: Puneet Harischandra Suvarna has collaborated with leading research institutions, universities, and innovative companies to bring his ideas to life, fostering a culture of innovation and progress.

Conclusion: Puneet Harischandra Suvarna stands as a beacon of inspiration in the world of inventions, with his relentless pursuit of excellence and passion for creating a better future through his groundbreaking innovations.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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