The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2019
Filed:
Oct. 13, 2017
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
Steven Bentley, Menands, NY (US);
Rohit Galatage, Clifton Park, NY (US);
Puneet Harischandra Suvarna, Menands, NY (US);
Assignee:
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 29/49 (2006.01); H01L 21/28 (2006.01); H01L 23/535 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 29/516 (2013.01); H01L 21/28079 (2013.01); H01L 23/535 (2013.01); H01L 29/495 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01); H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01);
Abstract
A layer of ferroelectric material is incorporated into the gate contact of a metal oxide semiconductor field effect transistor (MOSFET), i.e., outside of the device active area. Flexibility in the deposition and patterning of the ferroelectric layer geometry allows for efficient matching between the capacitance of the ferroelectric layer and the capacitance of the gate, providing a step-up voltage transformer, decreased threshold voltage, and a sub-threshold swing for the device of less than 60 mV/decade.